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Z8932120PSC Datasheet, PDF (9/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS
Zilog
Table 4. Z89391 84-Pin PLCC Pin IdentiÞcation
No. Symbol
1 RXD
2 EXT12
3 PA4
4 EXT13
5 PA5
6 EXT14
7 PA6
8 VSS
9 PA7
10 EXT15
11 /PA_EN
12 /EXTEN
13 EXT3
14 PA8
15 EXT4
16 PA9
17 VSS
18 EXT5
19 PA10
20 EXT6
21 PA11
22 EXT7
23 TXD
24 PA12
25 EXT8
26 PA13
27 EXT9
28 VSS
29 PA14
30 EXT10
31 PA15
32 VDD
33 VSS
34 PD0
35 EXT11
36 PD1
37 INT2
38 PD2
39 INT1
40 PD3
41 UI1
42 UI0
Function
Direction
Serial Input from CODEC
External Data 12
Program Address 4
External Data 13
Program Address 5
External Data 14
Program Address 6
Ground
Input
In/Output
Output
In/Output
Output
In/Output
Output
Program Address 7
Output
External Data 15
In/Output
Prog. Mem. Address Enable Input
Ext. Bus Enable
Input
External Data 3
In/Output
Program Address 8
Output
External Data 4
In/Output
Program Address 9
Output
Ground
External Data 5
Program Address 10
External Data 6
Program Address 11
External Data 7
Serial Output to CODEC
Program Address 12
External Data 8
Program Address 13
External Data 9
Ground
In/Output
Output
In/Output
Output
In/Output
Output
Output
In/Output
Output
In/Output
Program Address 14
External Data 10
Program Address 15
Power Supply
Output
In/Output
Output
Input
Ground
Program Data 0
External Data 11
Program Data 1
User Interrupt 2
Program Data 2
User Interrupt 1
Program Data 3
User Input 1
User Input 0
Input
In/Output
Input
Input
Input
Input
Input
Input
Input
Z89321/371/391
16-Bit Digital Signal Processors
Table 4. Z89391 84-Pin PLCC Pin IdentiÞcation
No. Symbol Function
Direction
43 SCLK CODEC Interface Clock In/Output
1
44 VDD
Power Supply
45 RD//WR R/W External Bus
Input
Output
46 PD4
Program Data 4
Input
47 WAIT
Wait State Input
Input
48 PD5
Program Data 5
Input
49 /RESET Reset
Input
50 PD6
Program Data 6
Input
51 EA0
External Address 0
Output
52 PD7
Program Data 7
Input
53 VDD
Power Supply
54 /ROMEN ROM Enable
Input
Input
55 EA1
External Address 1
Output
56 PD8
Program Data 8
Input
57 EA2
External Address 2
Output
58 PD9
Program Data 9
Input
59 VDD
60 PD10
Power Supply
Program Data 10
Input
Input
61 /DS
External Data Strobe
Output
62 CLK
Clock
Input
63 PD11
Program Data 11
Input
64 HALT
Stop Execution
Input
65 FS0
Frame Synch for CODEC In/Output
Interface 0
66 INT0
User Interrupt 0
Input
67 PD12
Program Data 12
Input
68 UO0
User Output 0
Input
69 PD13
Program Data 13
Input
70 UO1
User Output 1
Input
71 PD14
Program Data 14
Input
72 FS1
Frame Synch for CODEC In/Output
Interface 1
73 PD15
Program Data 15
Input
74 VSS
75 VDD
76 PA0
Ground
Power Supply
Program Address 0
Input
Output
77 VSS
78 EXT0
Ground
External Data 0
In/Output
79 PA1
Program Address 1
Output
80 EXT1
External Data 1
In/Output
81 PA2
Program Address 2
Output
82 EXT2
External Data 2
In/Output
83 PA3
Program Address 3
Output
84 VSS
Ground
Note: *Input or output is defined by interface mode selection.
DS97DSP0100
PRELIMINARY
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