Z8932120PSC Datasheet, PDF (23/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Zilog
Z89321/371/391
16-Bit Digital Signal Processors
PERIPHERAL OPERATION
Disabling Peripherals
Disabling a peripheral (CODEC Interface, Counter) allows
general-purpose use of the EXT address for the disabled
EXT5-1 before being transferred along the internal data
bus of the processor. This is accomplished by writing data
to EXT5-2.
1
peripheral. If the peripheral is not disabled, the EXT control
signals and EXT data are still provided, but transfer of data
Writing Data to CODEC Interface
on the EXT pins is not available (because internal transfers ^{Internal data is transferred from the internal data bus of the}
are being processed on the internal bus). Care must be ^{processor to the EXT5-2 register. The CODEC interface}
taken to ensure that control of the EXT bus does not cause ^{constantly transfers and receives data during normal oper-}
bus conflicts.
ation. Data to be transferred is loaded to EXT5-2 and is au-
tomatically serially transferred.
Reading Data from CODEC Interface*
External data is serially transferred into the CODEC inter-
face registers from an external CODEC. This serial data is
loaded into EXT5-2 (8- or 16-bit modes). Because the in-
Note: EXT5-1 and EXT5-2 are used in the example, but
this information applies equally to EXT6-1 and EXT6-2.
(Refer to Figure 20, CODEC Block Diagram.)
terface is double-buffered, data must be transferred to
Internal 16-Bit Bus
16
16
EXT7-1
EXT7-2
EXT7-1 CODEC Timer Register
EXT7-2 Wait-State Register
Figure 19. EXT7 Register ConÞguration
LOADING EXT7
Because EXT7 is double-buffered, a pair of writes are per-
formed when loading the EXT7 registers (Figure 19).
Interrupts
The Z89321 features three interrupts:
LD EXT7, #%54F4
LD EXT7, #%6CDA
LD @P0:0, EXT7
Loads CODEC Timer Register
Loads Wait-State Register
Reads EXT7-1 and places
data in RAM
INT0
INT1
INT2
General-Purpose
CODEC Interface
13-Bit Timer
If all peripherals are enabled, INT0 (general-purpose) can
be used.
DS97DSP0100
PRELIMINARY
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