Z8932120PSC Datasheet, PDF (22/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Z89321/371/391
16-Bit Digital Signal Processors
Zilog
The status register can always be read in its entirety. S15-
S10 are set/reset by hardware and can only be read by
software. S9-S0 control hardware looping and can be writ-
ten by software (Table 6).
Table 6. RPL Description
S2
S1
S0
Loop Size
0
0
0
256
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
S15-S12 are set/reset by the ALU after an operation. S11-
S10 are set/reset by the user inputs. S6-S0 are control bits
described in Table 5. S7 enables interrupts. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiple/shift op-
tion is used, then the shifter shifts the result three bits right.
This feature allows the data to be scaled and prevents
overflows.
PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.
External Register, EXT4-EXT7, are used by the CODEC
interface and 13-bit timer, the registers are reviewed in the
CODEC interface section.
N OV Z C UI1 UI0 SH3 OP IE UO1 UO0
RPL
S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
* The output value is the opposite of the status register content.
Figure 18. Status Register
Ram Pointer Loop Size
000
256
001
2
010
4
011
8
100
16
101
32
110
64
111
128
"Short Form Direct" bits
User Output 0-1*
Interrupt Enable
Overflow protection
MPY output arithmetically shifted
right by three bits
User Input 0-1 (Read Only)
Carry
Zero
Overflow
Negative
22
PRELIMINARY
DS97DSP0100