Z8932120PSC Datasheet, PDF (24/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Z89321/371/391
16-Bit Digital Signal Processors
CODEC Interface
The CODEC Interface provides direct-connect capabilities
for standard 8-, 16-bit CODECs. The interface also sup-
ports 8-bit PCM, 8-bit PCM with hardware m-law conver-
sion (m-law expansion is done in software), 16-bit Linear
and Crystal's Sigma-Delta Stereo CODEC modes. Regis-
ters are used to accommodate the CODEC Interface
(EXT5, EXT6 and EXT7). The CODEC interface provides
two Frame Sync signals, which allows two channels of
data for transmission/receiving.
CODEC Interface Hardware
The CODEC Interface hardware uses six 16-bit registers,
m-law compression logic and general-purpose logic to con-
trol transfers to the appropriate register (Figure 20).
Zilog
CODEC Interface Control Signals
SCLK (Serial Clock)
The Serial Clock provides a clock signal for operating the
external CODEC. A 4-bit prescaler is used to determine
the frequency of the output signal.
SCLK = (0.5* CLK)/PS where: CLK = System Clock
PS = 4-bit Prescaler*
* The Prescaler is an up-counter.
Note: An internal divide-by-two is performed before the
clock signal is passed to the Serial Clock prescaler.
16
EXT5-1
CLKIN
16
Data Bus
16
EXT6-1
CLKIN
16
16
m-Law
Compression
EXT7-1
16
16
EXT5-2
CLKIN
EXT6-2
CLKIN
CLKIN
TXD
CONTROL
LOGIC
RXD
Figure 20. CODEC Interface Block Diagram
EXT7-2
24
PRELIMINARY
DS97DSP0100