Z8932120PSC Datasheet, PDF (20/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Z89321/371/391
16-Bit Digital Signal Processors
Zilog
Hardware Stack. A six-level hardware stack is connected
to the D-Bus to hold subroutine return addresses or data.
The Call instruction pushes PC+2 onto the stack, and the
RET instruction pops the contents of the stack to the PC.
User Inputs. The Z89321 has two inputs, UI0 and UI1,
which may be used by Jump and Call instructions. The
Jump or Call tests one of these pins and if appropriate,
jumps to a new location. Otherwise, the instruction be-
haves like a NOP. These inputs are also connected to the
status register bits S10 and S11, which may be read by the
appropriate instruction (Figure 8).
User Outputs. The status register bits S5 and S6 connect
directly to UO0 and UO1 pins and may be written to by the
appropriate instruction. Note: The user output value is the
opposite of the status register content.
Interrupts. The Z89321 has three positive edge-triggered
interrupt inputs. An interrupt is acknowledged at the end of
an instruction execution. It takes two machine cycles to en-
ter an interrupt instruction sequence. The PC is pushed
onto the stack. A RET instruction transfers the contents of
the stack to the PC and decrements the stack pointer by
one word. The priority of the interrupts is INT0 = highest,
INT2 = lowest. INT1 is dedicated to the CODEC interface
and INT2 is dedicated to the 13-bit timer if both peripherals
are enabled. Note: The SIEF instruction enables the inter-
rupts. The SIEF instruction must be used before exiting an
interrupt routine since the interrupts are automatically dis-
abled when entering the routine.
Registers. The Z89321 has 19 physical internal registers
and up to eight user-defined external registers. The EA2-
EA0 determines the address of the external registers. The
signals are used to read from or write to the external reg-
isters /DS, WAIT, RD//WR.
I/O Bus. The processor provides a 16-bit, CMOS-compat-
ible bus. I/O Control pins provide convenient communica-
tion capabilities with external peripherals, and single-cycle
access is possible. For slower communications, an on-
board hardware wait-state generator can be used to ac-
commodate timing conflicts. Three latched I/O address
pins are used to access external registers. The EXT 4, 5,
6, 7 pins are used by the internal peripherals. Disabling a
peripheral allows access to these addresses for general-
purpose use.
CODEC Interface. The multi-compatible, dual CODEC in-
terface provides the necessary control signals for trans-
mission of CODEC information to the DSP processor. The
interface accommodates 8-bit PCM or 16-bit Linear CO-
DECs. Special compatibility with Crystal Semiconductor's
4215/4216 CODECs provides the necessary interface for
audio applications. Many general-purpose 8-, 16-bit A/Ds,
D/As are adaptable. The interface can also be used as a
high-speed serial port.
m-Law Compression. The 8-bit CODEC interface mode
provides m-law compression from 13-bit format to 8-bit for-
mat. Decompression is performed in software by use of a
128-word lookup table.
Timer. Two programmable timers are available. One is
dedicated to the CODEC interface, the other for general-
purpose use. When a time-out event occurs, an interrupt
request is generated. Single pass and/or continuous
modes are available. If the CODEC interface is not used,
both timers can be used for general-purpose.
Note: Wait-State Generator. An internal wait-state
generator is provided to accommodate slow external
peripherals. A single wait-state can be implemented
through control registers EXT7-2. For additional states, a
dedicated pin (WAIT) can be held High. The WAIT pin is
monitored only during execution of a read or write
instruction to external peripherals (EXT bus).
Note: A WAIT pin is not available on the 40-pin DIP
package.
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PRELIMINARY
DS97DSP0100