Z8932120PSC Datasheet, PDF (17/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Z89321/371/391
16-Bit Digital Signal Processors
TIMING DIAGRAMS (Continued)
Zilog
CLOCK
HALT
HHOLD
HSET
TCY
Figure 12. HALT Timing
CLOCK
/RESET
INTERNAL
RESET
EXECUTE
RD/WR
/DS
UO0-1
EA0-2
EXT0-15
PA0-15
RAM/
REGISTERS
TCY
RSET
RWIDTH
RRISE
Cycle 0
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Code Execution
Tri-Stated
Tri-Stated
Access Reset Vector
Intact*
* The RAM and hardware registers are left intact
during a warm reset. A cold reset will produce
random data in these locations. The status
register is set to zeroes in both cases.
Figure 13. RESET Timing
17
PRELIMINARY
DS97DSP0100