Z8932120PSC Datasheet, PDF (2/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Z89321/371/391
16-Bit Digital Signal Processors
The Z893XX DSPs are optimized to accommodate ad-
vanced signal processing algorithms. The 24 MIPS (maxi-
mum) operating performance and efficient architecture
provides real-time instruction execution. Compression, fil-
tering, frequency detection, audio, voice detection/synthe-
sis, and other vital algorithms can all be accommodated.
The Z89321/371/391 devices feature an on-board CO-
DEC interface, compatible with 8-bit PCM and 16-bit CO-
DECs for digital audio applications. Additionally, an on-
board wait-state generator is provided to accommodate
slow external peripherals.
For prototypes, as well as production purposes, the
Z89371 member of the DSP product family is a one-time
Zilog
pro-grammable (OTP) device with a 16 MHz maximum op-
erating frequency.
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V_CC
GND
Device
V_DD
V_SS
PA0-15
PD0-15
PDATA
PADDR
INT0-2
HALT
/RESET
CLK
Program
Control
Unit
Program
ROM/OTP
4096x16
Data RAM0
256x16
Data RAM1
256x16
DDATA
XDATA
X
Y
Multiplier
P
Shifter
P0
P1
P2
DP0-3
P0
P1
P2
DP4-6
ADDR ADDR
GEN0 GEN1
Arithmetic
Logic Unit
(ALU)
Accumulator
EA0-2
EXT0-15
/DS
WAIT
RD//WR
8/16-Bit,
Full Duplex,
10 MBPS
Serial Port
13-Bit Timer
User I/O
TXD
RXD
SCLK
FS0
FS1
UI1-0
UO1-0
Figure 1. Z89321/371/391 Functional Block Diagram
2
PRELIMINARY
DS97DSP0100