Z8932120PSC Datasheet, PDF (33/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Zilog
int1_
fs1
fs0
sclk
txd
rxd
64 bits transferred
Z89321/371/391
16-Bit Digital Signal Processors
1
Figure 32. CODEC Stereo Mode Timing Diagram
16-Bit General-Purpose Timer
The 13-bit counter/timer is available for general-purpose
use. When the counter counts down to the zero state, an
interrupt is received on INT2. If the counter is disabled,
EXT4 can be used as a general-purpose address. The
counting operation of the counter can be disabled by reset-
ting bit 14. Selection of the clock source allows the ability
to extend the counter value past the 13 bits available in the
control register. Use of the CODEC counter output can ex-
tend the counter to 26 bits (see Figure 33).
Note: Placing zeroes into the count value register does
not generate an interrupt. Therefore, it is possible to have
a single-pass option by loading the counter with zeroes
after the start of count.
The counter is defaulted to the enable state, but if it is not
needed, it can be disabled. However, once disabled, the
counter cannot be enabled unless a reset of the processor
is performed.
Example:
LD EXT, #%C008 ;1100 0000 0000 1000
; Enable Counter
; Enable Counting
; Clock Source = OSC/2
; Count Value = 1000 = 8
; Interrupt will occur every
16 clock cycles
DS97DSP0100
PRELIMINARY
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