Z8932120PSC Datasheet, PDF (27/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Zilog
REGISTERS
EXT7-1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z89321/371/391
16-Bit Digital Signal Processors
1
Note: The timer is an up-counter.
Example: EXT7-1 = #%x00D
EXT7-1 = #%x80F
EXT7-1 = #%xFFx
EXT7-1 = #%x000
OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz
OSC = 12.288 MHz, SCLK = 6.144 MHz, FSYNC = 48 kHz
No interrupt
Max interrupt period (667 ms for OSC = 12.288 MHz)
SCLK Prescaler (up-counter)
SCLK/FSYNC Ratio Prescaler (up-counter)
CODEC Mode
00 8-bit with hardware m-law
01 8-bit without hardware m-law
10 16-bit linear
11 Crystal CS4215 / CS4216
FSYNC
0 External Source*
1 Internal Source
CODEC 0 Disable/Enable
0 = Disable*
1 = Enable
* Default
Figure 24. CODEC Interface Control Register
DS97DSP0100
PRELIMINARY
27