Z8932120PSC Datasheet, PDF (19/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Zilog
Z89321/371/391
16-Bit Digital Signal Processors
FUNCTIONAL DESCRIPTION
Instruction Timing. Most instructions are executed in one Note that all inputs to the multiplier should be fractional
1 ^{machine cycle. Long immediate instructions and Jump or twoÕs-complement, 16-bit binary numbers (Figure 16). This}
Call instructions are executed in two machine cycles. A puts them in the range [Ð1 to 0.9999695], and the result is
multiplication or multiplication/accumulate instruction re- in 24 bits so that the range is [Ð1 to 0.9999999]. In addition,
quires a single cycle. Specific instruction cycle times are if 8000H is loaded into both X and Y registers, the resulting
described in the Condition Code section.
multiplication is considered an illegal operation as an over-
flow would result. Positive one cannot be represented in
Multiply/Accumulate. The multiplier can perform a 16-bit _{fractional notation, and the multiplier will actually yield the}
x 16-bit multiply, or multiply accumulate, in one machine _{result 8000H x 8000H = 8000H (Ð1 x Ð1 = Ð1).}
cycle using the Accumulator and/or both the X and Y in-
puts. The multiplier produces a 32-bit result, however, only ALU. The ALU has two input ports, one of which is con-
the 24 most significant bits are saved for the next instruc- nected to the output of the 24-bit Accumulator. The other
tion or accumulation. For operations on very small num- input is connected to the 24-bit P-Bus, the upper 16 bits of
bers where the least significant bits are important, the data which are connected to the 16-bit D-Bus. A shifter between
should first be scaled by eight bits (or the multiplier and the P-Bus and the ALU input port can shift the data by
multiplicand by four bits each) to avoid truncation errors. three bits right, one bit right, one bit left or no shift (Figure
17).
DDATA
XDATA
DDATA
16 16
X Register (16) Y Register (16)
Multiplier
P Register (24)
24
24
Shift Unit *
24
MUX
24
* Options:
1 Bit Right
3 Bits Right
No Shift
1 Bit Left
Figure 16. Multiplier Block Diagram
Mult. (24) Shift Unit *
24 24
16 24
MUX
* Options:
24 1 Bit Right
3 Bits Right
No Shift
1 Bit Left
24
Arithmetic Logic Unit (ALU)
24
Accumulator (24)
Figure 17. ALU Block Diagram
DS97DSP0100
PRELIMINARY
19