Z8932120PSC Datasheet, PDF (34/40 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSORS

Z89321/371/391
16-Bit Digital Signal Processors
ADDRESSING MODES (Continued)
Zilog
EXT4
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Count Value (Down-Counter)
* Default State
Clock Source
0 Oscillator/2*
1 CODEC Counter Output
Count Operation
0 = Disable*
1 = Enable
Counter
0 = Disable
1 = Enable*
Figure 33. CODEC Timer Register
ADDRESSING MODES
This section discusses the syntax of the addressing
modes supported by the DSP assembler.
Table 8. Addressing Modes
Symbolic Name
Syntax
Description
<pregs>
Pn:b
Pointer Register
<dregs> (Points to RAM)
Dn:b
Data Register
<hwregs>
X,Y,PC,SR,P , EXTn, A, BUS Hardware Registers
<accind> (Points to Program Memory @A
Accumulator Memory Indirect
<direct>
<expression>
Direct Address Expression
<limm>
#<const exp>
Long (16-bit) Immediate Value
<simm>
#<const exp>
Short (8-bit) Immediate Value
<regind> (Points to RAM)
@Pn:b
Pointer Register Indirect
@Pn:b+
Pointer Register Indirect with Increment
@Pn:bÐLOOP
Pointer Register Indirect with Loop Decrement
@Pn:b+LOOP
Pointer register Indirect with Loop Increment
<memind> (Points to Program Memory) @@Pn:b
Pointer Register Memory Indirect
@Dn:b
Data Register Memory Indirect
@@Pn:bÐLOOP
Pointer Register Memory Indirect with Loop
Decrement
@@Pn:b+LOOP
Pointer Register Memory Indirect with Loop
Increment
@@Pn:b+
Pointer Register Memory Indirect with Increment
34
PRELIMINARY
DS97DSP0100