DS593 Datasheet, PDF (31/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

Platform Cable USB II
Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals (Cont’d)
Pin
Number
JTAG
Configuration
MODE
SPI
Programming⁽¹⁾
Slave-Serial
Configuration
Direction⁽²⁾
8
–
–
Done
In
10
–
13
–
14
–
3, 5, 7, 9,
11
–
1, 12
–
–
DIN
Out
–
PGND
Out
–
INIT
In
–
–
–
–
–
–
Description
Slave Serial Configuration Done. This pin
indicates to Platform Cable USB II that
target FPGAs have received the entire
configuration bitstream and should be
connected to the Done pin on all FPGAs in
parallel for daisy-chained configurations.
Additional CCLK cycles are issued following
the positive transition of Done to insure that
the configuration process is complete.
Slave Serial Configuration Data Input.
This pin outputs the serial input data stream
for target FPGAs and should be connected
to the DIN pin of the target FPGA in a single-
device system, or to the DIN pin of the first
FPGA in a daisy-chain configuration.
Slave Serial Pseudo Ground. Use of this
pin is optional. PGND is pulled Low during
Slave Serial operations; otherwise, it is high-
Z. This pin is connected to an open-drain
driver and requires a pull-up resistor on the
target system.⁽⁴⁾
Slave Serial Configuration Initialization.
This pin indicates that configuration memory
is being cleared and should be connected to
the INIT_B pin of the target FPGA for a
single-device system, or to the INIT_B pin
on all FPGAs in parallel in a daisy-chain
configuration.
Digital Ground. All ground pins should be
connected to digital ground on the target
system to minimize crosstalk.
Not Connected.
Notes:
1. The listed SPI pin names match those of SPI flash devices from ST Microelectronics. Pin names of compatible SPI devices from other
vendors can vary. Consult the vendor's SPI device data sheet for equivalent pin names.
2. The signal pins (HALT_INIT_WP, TDI_DIN_MOSI, TDO_DONE_MISO, TCK_CCLK_SCK, TMS_PROG_SS) are bidirectional. Their
directions during cable operations are defined by the current configuration or programming mode (JTAG, SPI or Slave Serial).
3. The target reference voltage must be regulated and not have a current-limiting resistor in series with the V_REF pin.
4. For more details, see Target System Connections, page 15 and Pseudo Ground Signal, page 22.
Platform Cable USB II Operating Characteristics
Table 7: Absolute Maximum Ratings⁽¹⁾
Symbol
Description
Conditions
V_BUS
V_REF
I_REF
T_A
USB Port Supply Voltage
Target Reference Voltage
Target Supply Current
Ambient Operating Temperature
V_REF = 5.25V
Value
5.25
6.00
100
70
Units
V
V
mA
°C
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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