DS593 Datasheet, PDF (21/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

X-Ref Target - Figure 21
Platform Cable USB II
Input Receive Structure
V_REF Voltage (VDC)
Figure 21: Output Drive Voltage vs. V_REF
DS593_21_021408
Each input signal is routed through a NC7WZ07 ultra high-speed CMOS, open-drain receive buffer. Series-termination
resistors (499Ω) provide current limit protection for positive and negative excursions. Schottky diodes provide the input
buffers with undershoot protection. The receive buffers are biased by an internal 1.8V power supply. See Table 9, page 32
for V_IL and V_IH specifications. The receive buffers can tolerate voltages higher than the bias voltage without damage,
compensating for target system drivers in multi-device chains where the last device in the chain might be referenced to a
voltage other than V_REF (for example, the TDO output at the end of a JTAG chain).
X-Ref Target - Figure 22
To output buffer
FPGA
Input
NC7WZ07
499Ω
BAT54
2 mm Connector
I/O Pin
Figure 22: Target Interface Receiver Topology
DS593_22_021408
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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