DS593 Datasheet, PDF (23/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

X-Ref Target - Figure 24
Platform Cable USB II
DS593_24_021408
Figure 24: Enabling the HALT Signal in iMPACT (9.2i)
Timing Specifications
For JTAG, SPI, and Slave Serial configuration modes, the TDI_DIN_MOSI and TMS_PROG_SS outputs change on falling
edges of TCK_CCLK_SCK (Figure 25). Target devices sample TDI_DIN_MOSI and TMS_PROG_SS on rising edges of
TCK_CCLK_SCK. The minimum setup time T_TSU(MIN) for target device sampling of TDI_DIN_MOSI or TMS_PROG_SS is:
T_TSU(MIN) = T_CLK/2 – T_CPD(MAX)
= 20.8 ns – 16.0 ns
= 4.8 ns
where:
T_CLK/2 = TCK_CCLK_SCK low time at 24 MHz,
T_CPD(MAX) = Maximum TDI_DIN_MOSI or TMS_PROG_SS propagation delay relative to TCK_CCLK_SCK inherent in
the output stage of the cable.
Reducing the TCK_CCLK_SCK frequency increases the data setup time at the target.
Note: Timing specifications apply when V_REF = 3.3V. Operations at 24 MHz might not be possible when using a V_REF below 3.3V due to
the increased propagation delay through the output buffer stage of the cable.
TDO/MISO Timing Considerations
Designers of target systems must take care to observe specific timing requirements for TDO (JTAG chains) or MISO
(dedicated SPI in-system programming) when incorporating the 2-mm IDC connector. In particular, if an open-drain or open-
collector buffer is inserted between TDO (MISO) and the cable, the value of the pull-up resistor at the output of such buffers
must be relatively small (for example, less than 330Ω) to avoid delays associated with parasitic capacitance.
Figure 26, page 25 and Figure 27, page 26 show the timing relationship between TCK and TDO. The signal TDO_SMPL is
an internal logic signal not available at the target interface, but is shown to highlight the location of the TDO sampling point.
In Figure 26, the negative TCK transition at G1 causes the last device in the target system JTAG chain to drive TDO, which
propagates to the cable at G2. The time from G1 to G2 is the sum of the propagation delays in the driver stage of the target
device and the receiver stage of the cable (37 ns in this example).
In Figure 27, the cursors show the total setup time (42 ns) before TDO is sampled by the cable. Figure 28, page 27 is an
analog representation of the logical condition shown in Figure 26 and Figure 27 captured at the target system.
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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