DS593 Datasheet, PDF (17/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

Platform Cable USB II
Direct SPI
Platform Cable USB II can connect directly to a single SPI flash device. Figure 18, page 18 shows an example SPI flash
connection. XAPP951, Configuring Xilinx FPGAs with SPI Serial Flash provides additional details of the cable connections
necessary to program a FPGA bitstream into a SPI flash device.
Note: See Configuring Xilinx FPGAs with SPI Serial Flash for a list of supported SPI devices.
By connecting PGND to PROG_B of the FPGA (Figure 17), the FPGA can be commanded to set its SPI signals to high-Z
while the cable programs a SPI flash device. PGND is pulled Low when the cable is driving its SPI signals in SPI mode and
set to high-Z when the cable is not driving its SPI signals. PGND eliminates the need for a hardware jumper to ground on the
PROG_B signal and the need for additional control logic. PGND is controlled by an open-drain driver.
Note: PGND control for SPI programming is available in iMPACT versions 9.2i and later.
X-Ref Target - Figure 17
VCCAUX(2)
2-mm Connector
VCCAUX(2)
470Ω⁽⁴⁾
V_REF 2
DONE 8
PROG 4
DIN 10
INIT 14
CCLK 6
GND⁽³⁾ _*
PROG DONE
DIN FPGA₁ DOUT
V_CCO⁽²⁾
INIT CCLK⁽¹⁾
PROG DONE
DIN FPGA₂ DOUT
INIT CCLK⁽¹⁾
PROG DONE
DIN FPGA_n DOUT
INIT CCLK⁽¹⁾
DS593_17_021408
Notes:
1. Set Mode pins (M2-M0) on each FPGA to Slave-Serial mode when using the USB cable, so the CCLK is treated as an input.
2. Example uses generalized nomenclature for the voltages-supply levels. Refer to the device data sheet for the appropriate serial configuration
voltage-supply levels.
3. Attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9, and 11.
4. A pull-up is required when two or more devices are cascaded and programmed for open-drain operation.
Figure 17: Example of Cascaded Slave-Serial Topology
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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