DS593 Datasheet, PDF (24/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

Platform Cable USB II
Note: The propagation delay from TCK to TDO is 26 ns. Because Figure 26 shows a propagation delay of 37 ns, the difference of 11 ns
is attributable exclusively to input delays in the cable. At 12 MHz, there is still sufficient setup time before the cable samples prior to the
next negative TCK transition.
X-Ref Target - Figure 25
TMS_PROG changes on Negative
Edge of TCK_CCLK (G1)
TDI_DIN Changes
on Negative Edge
of TCK_CCLK (G2)
DS593_25_021408
Figure 25: TDI_DIN_MOSI and TMS_PROG_SS Timing with Respect to TCK_CCLK_SCK
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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