DS593 Datasheet, PDF(19/35 Page) Xilinx, Inc – Includes innovative FPGA-based acceleration

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DS593 Datasheet, PDF (19/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

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Platform Cable USB II

For a complete description on using Platform Cable USB II for indirect programming of third-BPI PROMs and for a complete

list of supported BPI PROMs, refer to XAPP973, Indirect Programming of BPI PROMs with Virtex-5 FPGAs.

Target Interface Reference Voltage and Signals

Target Reference Voltage Sensing (VREF)

Platform Cable USB II incorporates an over-voltage clamp on the VREF pin of the 2-mm ribbon cable connector. The

clamped voltage (VREF_CLAMP) supplies high-slew-rate buffers that drive each of the output signals (see Output Driver

Structure). VREF must be a regulated voltage.

Note: Do not insert a current-limiting resistor in the target system between the VREF supply and pin 2 on the 2-mm connector.

When Platform Cable USB II is idle, a nominal amount of current is drawn from the target system VREF. Figure 19 shows the

VREF current as a function of VREF voltage.

No damage to Platform Cable USB II occurs if the AâB cable is unplugged from the host while the ribbon cable or flying leads

are attached to a powered target system. Similarly, no damage to target systems occurs if Platform Cable USB II is powered

and attached to the target system while the target system power is off.

Bidirectional Signal Pins

Platform Cable USB II provides five bidirectional signal pins: TDI_DIN_MOSI, TDO_DONE_MISO, TCK_CCLK_SCK,

TMS_PROG_SS and HALT_INT_WP. Each pin incorporates the same I/O structure. The state of each pin (reading or

writing) is determined by the current mode of the cable (JTAG, SPI or Slave Serial).

Output Driver Structure

Each output signal is routed through a NC7SZ126 ultra high-speed CMOS buffer (Figure 20, page 20). Series-damping

resistors (30.1Î©) reduce reflections. Weak pull-up resistors (20 kÎ©) terminating at VREF_CLAMP maintain a defined logic level

when the buffers are set to high-Z. Schottky diodes provide the output buffers with undershoot protection.

The FPGA sets the output buffers to high-Z when VREF drops below 1.30 V. In addition, an over-voltage Zener on VREF

clamps VREF_CLAMP to approximately 3.9V.

Figure 21, page 21 shows the relationship between the output drive voltage and VREF.

Note: The output drivers are enabled only during cable operations; otherwise, they are set to high-Z between operations.

Xilinx design tools actively drive the outputs to logic 1 before setting the respective buffer to high-Z, avoiding the possibility

of a slow rise-time transition caused by a charge path through the pull-up resistor into parasitic capacitance on the target

system.

DS593 (v1.2.1) March 17, 2011

www.xilinx.com

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