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| DS593 Datasheet, PDF (16/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration | |||
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X-Ref Target - Figure 16
VCCAUX
Platform Cable USB II
TDO
TDI
TMS
TCK
2-mm VCCAUX(1)
Connector
VREF 2
TDO 8
TDI 10
TMS 4
TCK 6
PGND(5) 13
GND(2) *
(4)
A
Y
B
S
JTAG CHAIN
TDI
TMS
TDO
TCK
VCCAUX
Required
Pull-Up(3)
1 KΩ
(4)
A
Y
B
S (4)
A
Y
B
S
MUX Truth Table
S Output
H
Y=A
L
Y=B
DS593_16_021408
Notes:
1. Example implies that VCCO, VCCJ, and/or VCCAUX for various devices in the JTAG chain are set to the same voltage.
2. Attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9, and 11.
3. The cable uses an open-drain driver to control the pseudo ground (PGND) signal â an external pull-up resistor is required.
4. Assumes that the multiplexor supply voltages pins are connected to VCCAUX.
5. Pin 13 is grounded on legacy Xilinx USB cables (models DLC9, DLC9G and DLC9LP), and Parallel Cable IV (model DLC7). These cables
need to be manually detached from the 2-mm connector to allow the primary configuration source to have access to the JTAG chain.
Figure 16: Example Using PGND in a JTAG Chain
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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