DS593 Datasheet, PDF (15/35 Pages) Xilinx, Inc – Includes innovative FPGA-based acceleration

Platform Cable USB II
Target System Connections
This section provides examples of the various configuration topologies supported by Platform Cable USB II. Each example
incorporates the 2-mm connector (see Target Interface Connectors, page 14) as the cable interface. Diagrams in this section
provide a functional relationship between the cable interface and the target devices.
Note: Signal integrity is not considered in these examples. Refer to Signal Integrity, page 27 for details on buffering and termination.
JTAG and Slave Serial
Multiple devices can be cascaded when using either a JTAG or slave-serial topology in target systems. Figure 15 and
Figure 17, page 17 show typical routing for JTAG and Slave Serial topologies, respectively.
Platform Cable USB II provides a multi-use signal on its target interface connector called pseudo ground (PGND). The
PGND pin is connected to an open-drain driver (see Pseudo Ground Signal, page 22); hence, it is either Low or high-Z. The
behavior of PGND is determined by the host application connected to the cable. In iMPACT, PGND is active-Low during
JTAG, Slave Serial and SPI operations (for example, programming, configuration, read back, etc.) and high-Z when the cable
is idle.
Figure 16, page 16 shows a typical use of PGND as a control signal to manage a target system’s JTAG chain. PGND drives
the select (S) term on a set of multiplexers that switch between the primary configuration source and the cable. When PGND
is active-Low, the cable drives the JTAG chain. When PGND is high-Z, the primary configuration source drives the JTAG
chain. This capability allows Platform Cable USB II to remain attached to the target system while remaining isolated from the
primary configuration source. A similar scheme can be used with Slave Serial topologies.
PGND control is available only in iMPACT versions 10.1 and later. PGND remains high-Z in earlier versions of iMPACT and
in Xilinx design tools where the PGND signal is not supported.
The DONE pin on FPGAs can be programmed to be an open-drain or active driver. For cascaded Slave Serial topologies,
an external pull-up resistor should be used, and all devices should be programmed for open-drain operation.
X-Ref Target - Figure 15
2-mm Connector
V_CCAUX(1)
VREF 2
TDO 8
TDI 10
TMS 4
TCK 6
GND⁽²⁾ _*
ISP
TDI ^PROM TDO
TMS TCK
FPGA
TDI
TDO
TMS TCK
CPLD
TDI
TDO
TMS TCK
DS593_15_011508
Notes:
1. Example implies that V_CCO, V_CCJ, and V_CCAUX for various devices are set to the same voltage. Refer to the device data sheet for the
appropriate JTAG voltage-supply levels.
2. Attach the following 2-mm connector pins to digital ground: 3, 5, 7, 9, and 11.
Figure 15: Example of JTAG Chain Topology
DS593 (v1.2.1) March 17, 2011
www.xilinx.com
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