W83627HF Datasheet, PDF (69/185 Pages) Winbond – WINBOND I/O

W83627HF/F
PRELIMINARY
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode.
Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will
go to legacy UART mode and clear some register values shown table as follows.
TABLE :BAUD RATE TABLE
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Desired Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
1.5M
Decimal divisor used to
generate 16X clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
1 ^{Note 1}
Percent error difference between
desired and actual
**
**
0.18%
0.099%
**
**
**
**
**
0.53%
**
**
**
**
**
**
**
**
**
0%
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set.
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
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Publication Release Date: Sep 1998
Revision 0.50