W83627HF Datasheet, PDF (6/185 Pages) Winbond – WINBOND I/O

W83627HF/F
PRELIMINARY
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3).....................60
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL).......................................................................................60
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) .....................................................................................60
6. PARALLEL PORT ...............................................................................................................61
6.1 PRINTER INTERFACE LOGIC ..........................................................................................................................61
6.2 ENHANCED PARALLEL PORT (EPP) .............................................................................................................62
6.2.1 Data Swapper.................................................................................................................................................63
6.2.2 Printer Status Buffer .......................................................................................................................................63
6.2.3 Printer Control Latch and Printer Control Swapper..................................................................................64
6.2.4 EPP Address Port............................................................................................................................................64
6.2.5 EPP Data Port 0-3 ..........................................................................................................................................65
6.2.6 Bit Map of Parallel Port and EPP Registers.................................................................................................65
6.2.7 EPP Pin Descriptions ....................................................................................................................................66
6.2.8 EPP Operation ................................................................................................................................................66
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ...............................................................................67
6.3.1 ECP Register and Mode Definitions..............................................................................................................67
6.3.2 Data and ecpAFifo Port ................................................................................................................................68
6.3.3 Device Status Register (DSR) ........................................................................................................................68
6.3.4 Device Control Register (DCR)......................................................................................................................69
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.............................................................................................70
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011.....................................................................................................70
6.3.7 tFifo (Test FIFO Mode) Mode = 110 ...........................................................................................................70
6.3.8 cnfgA (Configuration Register A) Mode = 111...........................................................................................70
6.3.9 cnfgB (Configuration Register B) Mode = 111..........................................................................................70
6.3.10 ecr (Extended Control Register) Mode = all..............................................................................................71
6.3.11 Bit Map of ECP Port Registers ...................................................................................................................72
6.3.12 ECP Pin Descriptions..................................................................................................................................73
6.3.13 ECP Operation.............................................................................................................................................74
6.3.14 FIFO Operation ...........................................................................................................................................74
6.3.15 DMA Transfers.............................................................................................................................................75
6.3.16 Programmed I/O (NON-DMA) Mode ........................................................................................................75
6.4 EXTENSION FDD MODE (EXTFDD) ..............................................................................................................75
6.5 EXTENSION 2FDD MODE (EXT2FDD)..........................................................................................................75
7. KEYBOARD CONTROLLER ............................................................................................76
7.1 OUTPUT BUFFER................................................................................................................................................77
Publication Release Date:Sep 1998
-III -
Revision 0.50