W83627HF Datasheet, PDF (66/185 Pages) Winbond – WINBOND I/O

W83627HF/F
PRELIMINARY
Table: Low Frequency range select of receiver.
RX_FR2~0 (Low Frequency)
001
010
RX_FSL4~0
Min.
Max.
Min.
Max.
00010
26.1
29.6
24.7
31.7
00011
28.2
32.0
26.7
34.3
00100
29.4
33.3
27.8
35.7
00101
30.0
34.0
28.4
36.5
00110
00111
01000
01001
01011
31.4
32.1
32.8
33.6*
34.4
35.6
36.4
37.2
38.1*
39.0
29.6
30.3
31.0
31.7
32.5
38.1
39.0
39.8
40.8
41.8
01100
36.2
41.0
34.2
44.0
01101
01111
37.2
38.2
42.1
43.2
35.1
36.0
45.1
46.3
10000
10010
40.3
41.5
45.7
47.1
38.1
39.2
49.0
50.4
10011
10101
10111
42.8
44.1
45.5
48.5
50.0
51.6
40.4
41.7
43.0
51.9
53.6
55.3
11010
11011
11101
48.7
50.4
54.3
55.2
57.1
61.5
46.0
47.6
51.3
59.1
61.2
65.9
Note that the other non-defined values are reserved.
011
Min.
23.4
25.3
26.3
26.9
28.1
28.7
29.4
30.1
30.8
32.4
33.2
34.1
36.1
37.2
38.3
39.5
40.7
43.6
45.1
48.6
Max.
34.2
36.9
38.4
39.3
41.0
42.0
42.9
44.0
45.0
47.3
48.6
49.9
52.7
54.3
56.0
57.7
59.6
63.7
65.9
71.0
5.1.6 Bank0.Reg5 - UART Line Status Register (USR)
Power on default <7:0> = 0000,0000 binary
Bit
Name
7-3 Reserved
2 RX_TO
Read/Write
-
Read/Write
Description
-
Set to 1 when receiver FIFO or frame status FIFO occurs
time-out. Read this bit will be cleared.
1 OV_ERR
0 RDR
Read/Write
Read/Write
Received FIFO overrun. Read to clear.
This bit is set to a logical 1 to indicate received data are
ready to be read by the CPU in the RBR or FIFO. After no
data are left in the RBR or FIFO, the bit will be reset to a
logical 0.
- 56 -
Publication Release Date: Sep 1998
Revision 0.50