W89C926 Datasheet, PDF (5/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
Pin Description, continued
NAME
NUMBER
Memory Support Interface
MSA0-7 90-97
MSA8-10 82, 81, 78
MSA11-13 80, 98, 84
MSA14-16 99, 69, 70
MSD0-2
89-87
MSD3-7
71-75
RCS
77
EECS/
76
FCS
MSRD
79
TYPE
O/TTL
IO/3SH
I/O/3SH
O/TTL
O/3SH
I/3SH
O/TTL
DESCRIPTION
Memory Support Address:
Latched address used to decode accesses to the on-
board memory.
Memory Support Data Bus:
Bidirectional on-board memory data bus.
EEPROM Interface:
During the EEPROM auto-load or read/write sequence,
MSD0 is used as a serial data input/output from/to
EEPROM, MSD1 outputs EEPROM commands to
EEPROM, and MSD2 sends a clock with a period of 1.2
microseconds. This function is available only when
EECS/ FCS is low during H/W reset.
SRAM Chip Select:
RCS is asserted by the PENTIC+ for SRAM chip
enable during buffer memory access.
Nonvolatile Memory Chip Select:
EECS/ FCS is asserted by the PENTIC+ for chip enable
during nonvolatile memory access. It is active low for
flash memory enable and active high for EEPROM chip
enable.
Nonvolatile Memory Detection:
During H/W reset, the PENTIC+ will determine the
existing nonvolatile memory type by sampling the
voltage level on this pin. If this pin is externally pulled
high with a 470K ohm resistor, the PENTIC+ will
determine that the memory is a flash memory; if the pin
is pulled low with a 470K ohm resistor, it will determine
that the memory is an EEPROM.
Memory Support Read:
MSRD is asserted by the PENTIC+ to strobe read data
from the on-board memory. Both SRAM and flash
memory use MSRD as the read command strobe.
Publication Release Date: January 1996
-5-
Revision A1