W89C926 Datasheet, PDF (26/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
FIFO Logic
The SLCT has a 16-byte FIFO, which acts as an internal buffer to compensate for differences in the
transmission/reception speed of different DMAs. The FIFO has FIFO threshold pointers to determine
the level at which it should initiate a local DMA. The threshold levels, Which are different
for reception and transmission, are defined in the DCR register.
The FIFO logic also provides FIFO overrun and underrun signals for network management purposes.
If received packets are flooding into the FIFO but the SLCT still does not have bus authority, the
FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO,
it may be underrun. Either case results in a network error. FIFO overruns and underruns can be
prevented by changing the values of the FIFO thresholds.
Normally, the data in the FIFO cannot be read; reading FIFO data during normal operation may
cause WAIT to be asserted and the system to hang. In loopback mode, however, the SLCT allows
FIFO data to be read by byte in order to check the correctness of the loopback operation.
Receive Logic
The receive logic is responsible for receiving the serial network data and packing the data in
byte/word sequence. The receive logic thus has serial-to-parallel logic in addition to network
detection capability.
The PENTIC+ accepts both physical addresses and group addresses (multicast and broadcast ad-
dresses). The SLCT extracts the address field from the serial input data. It then determines if the
address is acceptable according to the configurations defined in the Receive Configuration Register
(RCR). If the address is not acceptable, the packet reception is aborted. If the address is acceptable,
the data packet is sent to the serial-to-parallel logic before being fed into the FIFO.
After receiving a data packet, the SLCT automatically adds four bytes of data receive status, next
packet pointer, and two bytes of receive byte count into the FIFO for network management purposes.
The receive status contains the status of the incoming packet, so that the system can determine if the
packet is desired. The next packet pointer points to the starting address of the next packet in the
local receive ring. The receive byte count is the length of the packet received by the SLCT. Note that
the receive byte count may be different from the "length" field specified in the Ethernet packet format.
These four bytes of data will be transferred to the local buffer with the last batch of the local DMA.
However, these four bytes are stored at the first four addresses of the packet.
Transmit Logic
The SLCT must be filled before transmission may begin. That is, the local DMA read must begin
before the SLCT starts transmission. The SLCT first transmits 62 bits of preamble, then two bits of
SFD, and then the data packet. The parallel-to-serial logic serializes the data from the FIFO into a
data packet. After the data packet, the SLCT optionally adds four bytes of cyclic redundancy code
(CRC) to the tail of the packet.
A protocol PLA determines the network operations of the PENTIC+. Collision detection, random back-
off, and auto retransmit are implemented in the transmit logic. The protocol PLA ensures that
the PENTIC+ follows the IEEE 802.3 protocol.
SNA Module
The PENTIC+ also contains a serial network adaptor (SNA), which adapts the non-return-to-zero
(NRZ) used in the core processor and host system to Manchester coded network symbols. Two kinds
of interfacing signals are provided in the PENTIC+: an AUI interface for Ethernet and a coaxial
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