W89C926 Datasheet, PDF (33/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
SRAM (upper and lower values are for 70 nS and 15 nS SRAMs, respectively)
SYMBOL
DESCRIPTION
MIN.
MAX.
T1
Read cycle time.
70
-
15
-
T2
MSA0-15 valid to MSD0-7 read data valid.
-
70
-
15
T3
MSD0-7 read data hold valid from MSA0-15
change.
5
-
3
-
T4
MSD0-7 read data hold from MSRD deasserted.
0
-
0
-
T5
RCS held valid after MSRD deasserted.
5
-
3
-
T6
MSA0-15 held valid after MSRD deasserted.
5
-
3
-
T7
RCS asserted to MSWR asserted
0
-
0
-
T8
MSWR pulse width
60
-
15
-
T9
RCS asserted to MSWR deasserted.
60
-
15
-
T10
MSA0-15 held valid after MSWR deasserted.
5
-
3
-
T11
MSD0-7 write data setup before MSWR
asserted.
35
-
10
-
T12
MSD0-7 write data hold after MSWR deasserted.
5
-
3
-
T13
Even byte MSWR deasserted to odd byte
MSWR asserted. (see note)
10
-
5
-
T14
RCS held valid after MSWR deasserted.
5
-
3
-
T15 Even byte address invalid to odd byte address
0
-
valid. (see note)
0
-
T16 Command recovery time.
30
-
10
-
Note: This timing is invalid for byte access, e.g, attribute memory reading on SRAM image.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
- 33 -
Publication Release Date: January 1996
Revision A1