W89C926 Datasheet, PDF (36/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
Attribute Memory Access, continued
SYMBOL
DESCRIPTION
T13 _{CE1,2 asserted to WE deasserted}
T14 _{WE pulse width}
T15
HA0-16, REG valid to read data valid (see note)
T16 _{CE1,2 asserted to read data valid (see note)}
T17 _{WAIT pulse width}
T18a _{OE deasserted to next WE asserted}
T18b _{WE deasserted to next OE asserted}
T19a Read cycle time
T19b Write cycle time
Note: These timings are specified when the PENTIC+ does not assert WAIT .
Common Memory Access
MIN.
180
150
-
-
-
10
10
300
250
MAX.
-
-
300
300
12
-
-
-
-
UNIT
nS
nS
nS
nS
µS
nS
nS
nS
nS
HA0-16
REG
CE1,2
OE
WE
WAIT
HD0-15
(Read)
HD0-15
(Write)
T16
REG high
T11
T12
T3
T13
T1
T3
T14
T7
T8
T10
T9
T15
Valid
T4
Valid
T6
T5
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