W89C926 Datasheet, PDF (21/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
The ADR register located at page3 04H of the core controller is used as a temporary register for
EEPROM read/write. When the EEPROM load-back sequence specified above is performed, the
content of the specified address will be overwritten by the new data. Note that since the EEPROM is
word-aligned, each time the sequence is performed one word of data is modified. The address range
available is from 00H to ffH. To make sure that the EEPROM is written correctly, the programmer can
use the following read-check process to read a word from a specified address in the EEPROM.
write (EEAR, EOS = 1 EW/ER = 0);
write (ADR, address);
wait ( );
repeat (
read(EEAR, EOS);
) until (EOS = 0);
read(ADR);
/* read word data */
/* The entire sequence should be consecutive or the process will be aborted. */
Note that data will be kept in the ADR until they are updated. That is, the data can be read out any
time afterwards unless new data have been written.
SRAM Physical Map
When an EEPROM is used for attribute memory storage, the 32K byte SRAM has two roles in the
PENTIC+ design: the first 16K bytes of SRAM serve as an Ethernet buffer ring, while the remainder is
used for temporary storage of Ethernet IDs and CIS storage (if EECS/FCS is pulled low). The
detailed physical mapping of the SRAM memory is shown in the table below. When a flash memory is
used, only a 16K byte SRAM is needed to serve as the Ethernet ring buffer.
SRAM Physical
Address
0000H-
3FFFH
4000H
4001H
4002H
4003H
4004H
4005H
4006H
4007H
4008H-
400DH
400EH
400FH
4010H-
41FBH
41FCH-
7FFFH
EECS/ FCS pull low
Ethernet
Buffer
ID0
ID1
ID2
ID3
ID4
ID5
Board Type (05H)
Checksum
-
57H
57H
CIS
-
EECS/ FCS pull high
Ethernet
Buffer
Unused
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Publication Release Date: January 1996
Revision A1