W89C926 Datasheet, PDF (17/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
CFB (Configuration Register B), continued
BIT
SYMBOL
DESCRIPTION
2
LNKEN Link Enable
Writing a "1" to this bit will disable the link pulse generation, auto media-
switching function, and link integrity check function. Writing a "0" to this bit
will enable these functions.
3
LNKSTS Link Status
This bit indicates the present link status. It is high if the PENTIC+ is in TPI
mode, the link checking is enabled, and the link integrity is good or if the
link checking is disabled; otherwise, it is low.
4
IO16CON IOIS16 Timing Control.
If this bit is set high, the IOIS16 signal will decode CE1,2 ; otherwise,
IOIS16 is decoded according to HA and REG (default).
5
FWEN Flash Write Enable.
The default setting for the flash memory is write-protected. If FWEN = 1,
the PENTIC+ allows the flash to be written to. The write command and
chip select signal is prohibited if FWEN = 0.
6
SRAMSEL SRAM Speed Select.
If SRAMSEL = 1, the SRAM-15 is selected. Otherwise, SRAM-70 is used.
The default is SRAM-70.
7
-
Reserved.
Special Control Register Set
These registers are used for special checking or EEPROM access control.
Signature Register (SR)
A signature register is used for identification so that the software driver can easily distinguish between
different chips. The content can be read out in toggled order as follows:
Access Address: AMBase + 00FF4H
Access Type: Attribute Memory Read
MSB
LSB
(2N)th time:
10001000 where N = 1, 2, ... (after H/W reset)
(2N-1)th time:
00000000
EEPROM Access Register (EEAR)
This register is located on page 3 and is used for EEPROM read/write access control. It is inhibited
when EECS/FCS is pulled high.
Access Address: IOBase + 02H
Access Type: I/O Read/Write
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Publication Release Date: January 1996
Revision A1