W89C926 Datasheet, PDF (4/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
Pin Description, continued
NAME
NUMBER
OE
35
CE1,2
39, 36
REG
11
IOIS16
100
INPACK
13
WAIT
17
RESET
19
TYPE
I/TTL
I/TTL
DESCRIPTION
Output Enable:
The OE line is asserted by the system to obtain
memory read data from the card memory. It has an
internal 100K ohm pull-high resistor.
Card Enable:
CE1,2 are asserted by the system for data bus width
control as shown below. These pins have an internal
100K ohm pull-high resistor.
CE2 CE HD15-HD8 HD7-HD0
0
0
Valid
Valid
0
1
Valid
High-Z
1
0
High-Z
Valid
1
1
High-Z
High-Z
I/TTL
O/TTL
O/TTL
O/TTL
I/TTL
Register & I/O selection:
REG is asserted by the system to access attribute
memory or I/O space. It remains high inactive for
common memory accesses. It has an internal 100K ohm
pull-high resistor.
16-bit I/O access:
Asserted by the PENTIC+ to inform the system that
current operation is a 16-bit I/O access.
Input Acknowledge:
Asserted by the PENTIC+ when it has been selected
and can respond to an I/O read cycle.
Wait State:
Asserted by the PENTIC+ to insert wait states into
current memory or I/O access cycles.
Card Reset:
A RESET pulse will initiate the PENTIC+'s initialization
procedure, including auto-ID/configuration loading,
register initialization, and state machine initialization.
The pulse width should be at least 500 nS to be
recognized as a valid reset. This pin has an internal
100K ohm pull-up resistor.
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