W89C926 Datasheet, PDF (22/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
Note that if EECS/FCS is pulled low, the CIS is stored in the SRAM starting at address 4010H. The
length of the CIS depends on the word count specified in the first byte of EEPROM. During a power-
on reset, the PENTIC+ will load the exact word count specified in the EEPROM rather than read in all
bytes in the EEPROM.
The PENTIC+ will automatically translate the address from the host if the host tries to read CIS. It will
translate the attribute memory address by assuming that the first CIS byte is stored at 00H of attribute
memory, the second CIS byte is stored at 02H, and so forth. Users should assign CIS accordingly, or
else the CIS may be lost.
Also note that for auto-load information write protection, the PENTIC+ will ignore any write operation
above 4000H of SRAM. If it is necessary to change the settings, users should do so by writing the
flash memory or EEPROM.
Minimal System Design
A low-cost, dedicated LAN card can be designed using the PENTIC+ chip, a 32K x 8 SRAM, a serial
EEPROM (93C66/93CS66), and a pig tail for the network interface MAU, along with certain other
peripheral components. The following is a sample CIS table that can be used with this minimal
system design:
01 03 dc 03 ff
17 03 5b 09 ff
1a 05 01 01 e0 1f 0f
1b 13 c1 c1 7d 19 55 15 26 00 33 43 16 45 70 ff ff 48 40 00 00
14 00
f0 09 'WinICard' ff
21 02 06 03
20 04 u00 u01 u02 u03
15 14 04 01 u04 u05 u06 u07 u08 u09 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 00 ff
ff ff
FLASH MEMORY ACCESS
The flash access and the buffer SRAM share the same memory support bus. The address pins of the
flash memory are directly connected to MSA bus and data are accessed through the MSD bus.
EECS/FCS is active low if it is pulled high and the attribute memory is accessed in the range 00000H
to 03FFFH or the common memory is accessed in the range 04000H to 1FFFFH. Note that
CFB.FWE should be set to 1 before a flash write command is issued.
I/O MODE OPERATION
The I/O mode provides two DMA channels for system access. The remote DMA moves data between
system memory space and local memory space. The local DMA moves data between the FIFO of the
SLCT and local memory space. However, since the SLCT can handle local DMA operations
without system intervention (refer to the data sheet for the SLCT), the system has to perform only re-
mote DMA reads/writes.
In a transmit operation, the data should first be moved from the system to local buffer memory. This
is simply an "OUT" command on the PC. Then the system orders the SLCT to start transmission, and
the local DMA starts to move data from buffer memory to the transmit FIFO for transmission.
In a receive operation, the local DMA moves received data from the receive FIFO to the buffer and
asserts IREQ to the system when the buffer ring needs to be serviced. The system must move data
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