W89C926 Datasheet, PDF (40/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
PCMCIA bus slave access, continued
SYMBOL
DESCRIPTION
T16b _{IORD, IOWR deasserted to HA0-16 deasserted.}
T17 _{HA0-16 deasserted to IOIS16 deasserted. Note 4}
T18 _{IORD deasserted to INPACK deasserted.}
T19
MSA0-14 asserted t0 WAITdeasserted.
Note 1
T20
CE1,2 asserted to RCS asserted.
MIN.
20
-
-
-
-
MAX.
-
30
40
265
265
UNIT
nS
nS
nS
nS
nS
T21 _{OE, asserted to ROE asserted.}
Note 2
-
215
nS
T22 MSD odd byte read data valid to HD0-15 read data
-
valid.
35
nS
T23a
MSD odd byte read data hold after MSRD
deasserted.
5
-
nS
T23b _{MSD odd byte read data hold after MSRD}
3
deasserted.
Note.10
-
nS
T24
MSA0-14 valid to MSWR asserted.
0
-
nS
T25
second MSWR asserted before WAIT deasserted.
-
140
nS
Note 1
T26a _{MSD write data setup before MSWR deasserted.}
35
-
nS
T26b _{MSD write data setup before MSWR deasserted.}
10
-
nS
Note.10
T27a _{MSD write data hold after MSWR deasserted.}
5
-
nS
T27b _{MSD write data hold after MSWR deasserted. Note.10}
3
-
nS
T28 Command deasserted to next command asserted
150
-
nS
Notes: 1. This is the timing for insert wait states. WAIT is asserted if the core cannot service the access immediately; it will hold
asserted until the core is ready, causing the system to insert wait states.
2. This is the timing for shared memory access.
3. This is the timing for I/O access.
4. IOIS16 is asserted for 16-bit I/O transfers.
5. Read data valid is referenced to WAIT when wait states are inserted.
6. If no wait states are inserted, read data valid can be referenced from OE, IORD.
7. REG is asserted for I/O access and it is deasserted for common memory access.
8. INPACK is asserted only for I/O read operation.
9. This is a shared memory access without bus contention.
10. This is the timing for SRAM-15.
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