W89C926 Datasheet, PDF (14/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
F/ EE = 0 (EEPROM used)
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE
NAME
00000H
003D6H
Attribute/
(Note)
CIS
(492x 8)
Notes:
1. This attribute memory is an image from EEPROM. It is physically resident in upper half of the SRAM after power-on auto-
loading.
2. Refer to "Attribute Memory Mapping" for detailed locations.
3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter
and the socket service to determine.
REGISTER FILE
The W89C926 PENTIC+ has four register sets: the core register set, the PCMCIA configuration
register set, the LAN configuration register set, and the special control register set. The core register
set is the same as that in the W89C90 and will not be discussed here. The other three register sets
are described below.
PCMCIA Configuration Register Set
The PENTIC+ provides three PCMCIA configuration registers needed to ensure compatibility with
various operating systems.
COR (Configuration Option Register)
Access Address: AMBase + 00FD0H
Access Type: Attribute Memory Read/Write
BIT
SYMBOL
DESCRIPTION
0-5
IDX0-5 Configuration Index
These six bits are used to indicate entry of the card configuration table
located in the CIS (Card Information Structure; refer to PCMCIA R2.1).
These bits are 0 at power-on.
6
-
Reserved, must be 1 (level mode interrupt) when read.
7
SRESET S/W Reset
A software reset is issued when a 1 is written to this bit. This is the same
as a H/W reset except that this bit and the necessary information (CFA,
CFB, CIS, and Ethernet ID) are not cleared, and the auto-load procedure
is not performed. Returning a 0 to this bit will leave the PENTIC+ in a
post-reset state the same as that following a hardware reset. The value of
this bit at power-on is 0.
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