W89C926 Datasheet, PDF (28/48 Pages) Winbond – PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER

W89C926 PENTIC+
Collision Detection
The collision detection logic determines when transmit and receive signals occur simultaneously on
the twisted pair cable. Collisions will not be reported when the device is in a link-fail state.
The collision signal is also generated when the transceiver has detected a jabber condition or when
the SQE test is being performed.
SQE Test
The Signal Quality Error (SQE) test is used to test the collision signaling circuitry in the twisted-pair
transceiver module. After each packet transmission, an SQE signal is sent to the SLCT. The
SLCT expects this signal and will flag an error if it does not exist.
Jabber
The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for
greater than 26.2 mS. The jabber will re-enable the transmitter after the SLCT has been idle for at
least 420 mS.
Link Integrity
During periods of inactivity, link pulses are generated and received by both MAUs at either end of the
twisted pair to ensure that the cable has not been broken or shorted. A positive, 100 nS link integrity
signal is generated by the twisted-pair transceiver and transmitted on the twisted pair cable every 13
mS during periods of no transmission activity. The PENTIC+ assumes a link-good state if it detects
valid link pulse activity on the twisted-pair transceiver receive circuit. If neither receive data nor a link
pulse (positive or negative) is detected within 105 mS, the PENTIC+ enters a link-fail state. When a
link-fail condition occurs, four consecutive positive link pulses (or eight negative link pulses) must be
received before a link-good condition is assumed.
LCE CORE REGISTERS
This section lists the access addresses and access types of the LCE core registers. Refer to the
W89C90 or W89C901 data sheet for more detailed information.
Page 0 Address Assignments (PS1 = 0, PS0 = 0)
RA0-3
READ
WRITE
00 Command (CR)
Command (CR)
01 Current Local DMA Address 0 (CLDA0)
Page Start Register (PSTART)
02 Current Local DMA Address 1 (CLDA1)
Page Stop Register (PSTOP)
03 Boundary Pointer (BNRY)
Boundary Pointer (BNRY)
04 Transmit Status Register (TSR)
Transmit Page Start Address (TPSR)
05 Number of Collisions Register (NCR)
Transmit Byte Count Register 0 (TBCR0)
06 FIFO (FIFO)
Transmit Byte Count Register 1 (TBCR1)
07 Interrupt Status Register (ISR)
Interrupt Status Register (ISR)
08 Current Remote DMA Address 0 (CRDA0) Remote Start Address Register 0 (RSAR0)
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