W632GU6KB Datasheet, PDF (23/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
8.3.3.1 Partial Array Self Refresh (PASR)
If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified
address range shown in Figure 7 will be lost if Self Refresh is entered. Data integrity will be
maintained if tREFI conditions are met and no Self Refresh command is issued.
8.3.3.2 CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 7. CAS Write Latency is
the delay, in clock cycles, between the internal Write command and the availability of the first bit of
input data.
DDR3L SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined
as Additive Latency (AL) + CAS Write Latency (CWL); WL = AL + CWL. For more information on the
supported CWL and AL settings based on the operating clock frequency, refer to section 10.15
“Speed Bins” on page 133. For detailed Write operation refer to section 8.14 “WRITE Operation” on
page 56.
8.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT)
DDR3L SDRAM must support Self Refresh operation at all supported temperatures. Applications
requiring Self Refresh operation in the Extended Temperature Range must use the ASR function or
program the SRT bit appropriately.
When ASR enabled, DDR3L SDRAM automatically provides Self Refresh power management
functions for all supported operating temperature values. If not enabled, the SRT bit must be
programmed to indicate TOPER during subsequent Self Refresh operation.
ASR = 0, Self Refresh rate is determined by SRT bit A7 in MR2.
ASR = 1, Self Refresh rate is determined by on-die thermal sensor. SRT bit A7 in MR2 is don't care.
8.3.3.4 Dynamic ODT (Rtt_WR)
DDR3L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further
enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3L
SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10
configure the Dynamic ODT settings. In Write leveling mode, only Rtt_Nom is available. For details on
Dynamic ODT operation, refer to section 8.19.3 “Dynamic ODT” on page 83.
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Publication Release Date: Jan. 20, 2015
Revision: A06