W632GU6KB Datasheet, PDF (156/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
Table 54 – Derating values for DDR3L-1333/1600 tDS/tDH - (AC135)
DQ
Slew
rate
(V/nS)
4.0 V/nS
ΔtDS ΔtDH
ΔtDS, ΔtDH derating in [pS] AC/DC based^*
Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
DQS, DQS# Differential Slew Rate
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0
68
45
68
45
68
45
-
-
-
-
-
-
-
-
1.5
45
30
45
30
45
30
53
38
-
-
-
-
-
-
1.0
0
0
0
0
0
0
8
8
16
16
-
-
-
-
0.9
-
-
2
-3
2
-3
10
5
18
13
26
21
-
-
0.8
-
-
-
-
3
-8
11
1
19
9
27
17
35
27
0.7
-
-
-
-
-
-
14
-5
22
3
30
11
38
21
0.6
-
-
-
-
-
-
-
-
25
-4
33
4
41
14
0.5
-
-
-
-
-
-
-
-
-
-
29
-6
37
4
0.4
-
-
-
-
-
-
-
-
-
-
-
-
30 -11
Note: Cell contents ‘-’ are defined as not supported.
Table 55 –Derating values for DDR3L-1866 tDS/tDH - (AC130)
1.0 V/nS
ΔtDS ΔtDH
-
-
-
-
-
-
-
-
-
-
46
37
49
30
45
20
38
5
ΔtDS, ΔtDH derating in [pS] AC/DC based^*
DQ
Alternate AC130 Threshold -> VIH(AC)=VREF(DC)+130mV, VIL(AC)=VREF(DC)-130mV
Slew
DQS, DQS# Differential Slew Rate
rate
(V/nS) ^{8.0 V/nS 7.0 V/nS 6.0 V/nS 5.0 V/nS 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS 1.2 V/nS 1.0 V/nS}
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
4.0 33 23 33 23 33 23 - - - - - - - - - - - - - - - - - -
3.5 28 19 28 19 28 19 28 19 - - - - - - - - - - - - - - - -
3.0 22 15 22 15 22 15 22 15 22 15 - - - - - - - - - - - - - -
2.5 - - 13 9 13 9 13 9 13 9 13 9 - - - - - - - - - - - -
2.0 - - - - 0 0 0 0 0 0 0 0 0 0 - - - - - - - - - -
1.5 - - - - - - -22 -15 -22 -15 -22 -15 -22 -15 -14 -7 - - - - - - - -
1.0 - - - - - - - - -65 -45 -65 -45 -65 -45 -57 -37 -49 -29 - - - - - -
0.9 - - - - - - - - - - -62 -48 -62 -48 -54 -40 -46 -32 -38 -24 - - - -
0.8 - - - - - - - - - - - - -61 -53 -53 -45 -45 -37 -37 -29 -29 -19 - -
0.7 - - - - - - - - - - - - - - -49 -50 -41 -42 -33 -34 -25 -24 -17 -8
0.6 - - - - - - - - - - - - - - - - -37 -49 -29 -41 -21 -31 -13 -15
0.5 - - - - - - - - - - - - - - - - - - -31 -51 -23 -41 -15 -25
0.4 - - - - - - - - - - - - - - - - - - - - -28 -56 -20 -40
Note: Cell contents ‘-’ are defined as not supported.
Table 56 – Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition
Slew Rate [V/nS]
> 2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
< 0.5
DDR3L-1333/1600 (AC 135)
tVAC [pS]
Min.
Max.
113
-
113
-
90
-
45
-
30
-
11
-
Note
-
Note
-
Note
-
Note
DDR3L-1866 (AC 130)
tVAC [pS]
Min.
Max.
95
-
95
-
73
-
30
-
16
-
Note
-
-
-
-
-
-
-
-
-
Note: Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than
VIL(AC) level.
- 156 -
Publication Release Date: Jan. 20, 2015
Revision: A06