W632GU6KB Datasheet, PDF (158/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage can be
reduced to the 1.35V operating range provided that:
 Just prior to reducing the 1.5V operating voltages, no further commands are issued, other than
NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
 The 1.35V operating voltages are stable prior to issuing new commands, other than NOPs or
COMMAND INHIBITs.
 The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to any READ
command.
 The ZQ calibration is performed. tZQinit must be satisfied after the 1.35V operating voltages are
stable and prior to any READ command.
After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the
DDR3L and DDR3 levels, provided the sequence in Figure 111 is maintained.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
CK, CK#
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
Tmin = 10 ns
tCKSRX
RESET#
CKE
Command
Tmin = 10 ns
Tmin = 200 µs
T = 500 µs
Tmin = 10 ns
tIS
tXPR
tIS
tMRD
tMRD
tMRD
tDLLK
tMOD
*1
MRS
MRS
MRS
MRS
ZQCL
Tj
tZQinit
*1
Tk
VALID
VALID
BA
ODT
MR2
MR3
MR1
MR0
tIS
Static LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
VALID
tIS
VALID
RTT
TIME BREAK
DON'T CARE
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 111 –VDDQ/VDDQ Voltage Switch between DDR3L and DDR3
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Publication Release Date: Jan. 20, 2015
Revision: A06