W632GU6KB Datasheet, PDF (103/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
Table 20 – Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#
DDR3L-1333/1600
DDR3L-1866
Slew Rate
[V/nS]
tDVAC [pS] @
|VIH/LDIFF(AC)| =
320mV
tDVAC [pS] @
|VIH/LDIFF(AC)| =
270mV
tDVAC [pS] @
|VIH/LDIFF(AC)| =
270mV
tDVAC [pS] @
|VIH/LDIFF(AC)| =
250mV
tDVAC [pS] @
|VIH/LDIFF(AC)| =
260mV
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
> 4.0
189
-
201
-
163
-
168
176
-
4.0
189
-
201
-
163
-
168
3.0
162
-
179
-
140
-
147
176
-
154
-
2.0
109
-
134
-
95
-
105
111
-
1.8
91
-
119
-
80
-
91
1.6
69
-
100
-
62
-
74
1.4
40
-
76
-
37
-
52
97
-
78
-
56
-
1.2
Note
-
44
-
5
-
22
24
-
1.0
Note
-
Note
-
Note
-
Note
< 1.0
Note
-
Note
Note
-
Note
Note
-
Note
-
Note:
Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less
than VIL(AC) level.
10.6.4 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQSL, DQSU, CK#, DQSL#, DQSU#) has also
to comply with certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the AC-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
DQSL, DQSU, DQSL#, DQSU# have to reach VSEHmin / VSELmax (approximately the AC-levels
(VIH.DQ(AC) / VIL.DQ(AC) ) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC135)/VIL.CA(AC135) is used for ADD/CMD signals, then these AC-levels apply also for the
single-ended signals CK and CK#.
Table 21 – Single-ended levels for CK, DQSL, DQSU, CK#, DQSL# or DQSU#
PARAMETER
SYMBOL
DDR3L-1333/1600/1866
MIN.
MAX.
UNIT NOTES
Single-ended high level for strobes
Single-ended high level for CK, CK#
VSEH
(VDD/2) + 0.160
(VDD/2) + 0.160
Note 3
Note 3
V
1, 2
V
1, 2
Single-ended low level for strobes
Single-ended low level for CK, CK#
VSEL
Note 3
Note 3
(VDD/2) - 0.160
V
1, 2
(VDD/2) - 0.160
V
1, 2
Notes:
1. For CK, CK# use VIH.CA(AC) / VIL..CA(AC) of ADD/CMD; for strobes (DQSL, DQSL#, DQSU, DQSU#) use VIH.DQ(AC) /
VIL.DQ(AC) of DQs.
2. VIH.DQ(AC) / VIL.DQ(AC) for DQs is based on VREFDQ; VIH.CA(AC) / VIL.CA(AC) for ADD/CMD is based on VREFCA; if a
reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need to be within
the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and
undershoot. Refer to section 10.12 “Overshoot and Undershoot Specifications” on page 120.
- 103 -
Publication Release Date: Jan. 20, 2015
Revision: A06