W632GU6KB Datasheet, PDF (157/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
11. Backward Compatible to 1.5V DDR3 SDRAM VDD/VDDQ Requirements
11.1 Input/Output Functional
Symbol
VDD
VDDQ
Type
Supply
Supply
Function
Power Supply: DDR3L operation = 1.283V to 1.45V;
DDR3 operation = 1.425V to 1.575V
DQ Power Supply: DDR3L operation = 1.283V to 1.45V;
DDR3 operation = 1.425V to 1.575V
11.2 Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol Parameter/Condition
Min.
Typ.
Max.
Unit Notes
VDD Supply Voltage
1.283
1.35
1.45
V
1, 2, 3, 4
VDDQ Supply Voltage for Output
1.283
1.35
1.45
V
1, 2, 3, 4
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long
period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specifcation.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are
changed for DDR3 operation (see Figure 111).
11.3 Recommended DC Operating Conditions - DDR3 (1.5V) operation
Symbol Parameter/Condition
Min.
Typ.
Max.
Unit Notes
VDD Supply Voltage
1.425
1.5
1.575
V
1, 2, 3
VDDQ Supply Voltage for Output
1.425
1.5
1.575
V
1, 2, 3
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5 V operation, this DDR3L device operates to the DDR3 specifcations under the same speed timings as defined for
this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are
changed for DDR3L operation (see Figure 111).
11.4 VDDQ/VDDQ Voltage Switch between DDR3L and DDR3
If the SDRAM is powered up and initialized for the 1.35V operating voltage range, voltage can be
increased to the 1.5V operating range provided that:
 Just prior to increasing the 1.35V operating voltages, no further commands are issued, other than
NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
 The 1.5V operating voltages are stable prior to issuing new commands, other than NOPs or
COMMAND INHIBITs.
 The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to any READ
command.
 The ZQ calibration is performed. tZQinit must be satisfied after the 1.5V operating voltages are
stable and prior to any READ command.
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Publication Release Date: Jan. 20, 2015
Revision: A06