W632GU6KB Datasheet, PDF (148/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
10.16.4 Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the
datasheet tIS(base) and tIH(base) value (see Table 48) to the ΔtIS and ΔtIH derating value (see Table 49
and Table 51) respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(DC) to AC
region’, use nominal slew rate for derating value (see Figure 107). If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(DC) to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for derating value (see Figure 109).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual
signal is always later than the nominal slew rate line between shaded ‘DC to VREF(DC) region’, use
nominal slew rate for derating value (see Figure 108). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded ‘DC to VREF(DC) region’, the slew rate of a tangent line to the
actual signal from the DC level to VREF(DC) level is used for derating value (see Figure 110).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see
Table 52).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached VIH/IL(AC) at the time of the rising clock transition, a valid input signal is still required to
complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 48 – ADD/CMD Setup and Hold Base-Values for 1V/nS
Symbol
Reference
DDR3L-1333 DDR3L-1600 DDR3L-1866 Unit Note
tIS(base) AC160 VIH/L(AC) : SR=1 V/nS
80
60
-
pS
1
tIS(base) AC135 VIH/L(AC) : SR=1 V/nS
250
185
65
pS 1, 2
tIS(base) AC125 VIH/L(AC) : SR=1 V/nS
-
-
150
pS 1, 3
tIH(base) DC90 VIH/L(DC) : SR=1 V/nS
150
130
110
pS
1
Notes:
1. (AC/DC referenced for 1V/nS Address/Command slew rate and 2 V/nS differential CK-CK# slew rate)
2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 100pS for
DDR3L-1333/1600 of derating to accommodate for the lower alternate threshold of 135 mV and another 25 pS to account
for the earlier reference point [(160 mV - 135 mV) / 1 V/nS].
3. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 pS for
DDR3L-1866 of derating to accommodate for the lower alternate threshold of 135 mV and another 10 pS to account for the
earlier reference point [(135 mV - 125 mV) / 1 V/nS].
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Publication Release Date: Jan. 20, 2015
Revision: A06