W632GU6KB Datasheet, PDF (20/160 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3L SDRAM

W632GU6KB
8.3.2 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength,
Rtt_Nom impedance, additive latency, Write leveling enable and Qoff. The Mode Register 1 is written
by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling
the states of address pins according to the Figure 6 below.
BA2 BA1 BA0 A13 A12 A11 A10
A9 A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*¹
0
1
0*¹ Qoff
0*¹
0*¹ Rtt_Nom 0*¹ Level Rtt_Nom D.I.C
WR AL BT Rtt_Nom D.I.C DLL Mode Register 1
BA1
0
0
1
1
BA0
0
1
0
1
MR Select
MR0
MR1
MR2
MR3
A7 Write leveling enable
0
Disabled
1
Enabled
A12
Qoff^*2
0
Output buffer enabled
1
Output buffer disabled^*2
A9
A6
A2
Rtt_Nom^*3
0
0
0 Rtt_Nom disabled
0
0
1
RZQ/4
0
1
0
RZQ/2
0
1
1
RZQ/6
1
0
0
RZQ/12*⁴
1
0
1
RZQ/8*⁴
1
1
0
Reserved
1
1
1
Reserved
Note: RZQ = 240 ohms
A0
DLL Enable
0
Enable
1
Disable
Output Driver
A5
A1 _{Impedance Control}
0
0
RZQ/6
0
1
RZQ/7
1
0
Reserved
1
1
Reserved
Note: RZQ = 240 ohms
A4
A3 Additive Latency
0
0
0 (AL disabled)
0
1
CL-1
1
0
CL-2
1
1
Reserved
Notes:
1. BA2, A8, A10, A11 and A13 are reserved for future use and must be programmed to “0” during MRS.
2. Outputs disabled - DQs, DQSs, DQS#s.
3. In Write leveling Mode (MR1 A[7] = 1) with MR1 A[12]=1, all Rtt_Nom settings are allowed; in Write Leveling Mode (MR1 A[7]
= 1) with MR1 A[12]=0, only Rtt_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
4. If Rtt_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Figure 6 – MR1 Definition
8.3.2.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization,
and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on)
with MR1 (A0 = 0), the DLL is automatically disabled when entering Self Refresh operation and is
automatically re-enabled upon exit of Self Refresh operation. Any time the DLL is enabled and
subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK,
CKE must continuously be registered high. DDR3L SDRAM does not require DLL for any Write
operation, except when Rtt_WR is enabled and the DLL is required for proper ODT operation. For more
detailed information on DLL Disable operation refer to section 8.6 “DLL-off Mode” on page 25.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be
disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
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Publication Release Date: Jan. 20, 2015
Revision: A06