VSC7212 Datasheet, PDF (31/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

VIITTEESSSSEE
SEEMMIICCOONNDDUUCCTTOORRCCOORPROPROARTAIOTNION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Pin
29
27
28
38
39
45
79
78
77
74
80
40
41
12
15
16,24,32
42,84,94
6,11,19,33
44,83,93
49,57,64
70
47,54,59
62,67,72
3
8
1,25,26
50,51,75
76,100
Name I/O Type
Pin Description
Frequency LOCKed Mode. When HIGH indicates that the transmitting
FLOCK
I
TTL
device’s REFCLK is frequency-locked to the receiver’s word clock.
Controls rate matching (IDLE delete/duplicate) logic along with the WSI
input as defined in Table 6.
BIST
Built-In Self Test Mode. When HIGH, the transmitter continuously sends a
I
TTL 256 byte incrementing data pattern, and the receiver signals correct
reception of the test pattern with a LOW on TBERR.
ENcoder/DECoder Enable. When HIGH the VSC7212 is configured for 8
ENDEC
I
TTL bit operation, internal 8B/10B encoding is enabled. When LOW, a 10-bit
interface is used and internal 8B/10B encoding is bypassed.
RESETN
I
TTL
RESETN Input. When asserted LOW, the transmitter input skew buffer and
receiver elastic buffer are recentered.
WSI
I
TTL
Word Sync Input. Used to control chip-to-chip alignment and IDLE
character insertion/deletion as defined in Table 6.
WSO
O
TTL
Word Sync Output. Used to set initial chip-to-chip word alignment, and to
maintain alignment by controlling IDLE character insertion/deletion.
TCK
I
TTL JTAG Test Access Port Test Clock Input
TMS
I
TTL JTAG Test Access Port Test Mode Select Input
TDI
I
TTL JTAG Test Access Port Test Data Input
TDO
TRSTN
RSVD0
RSVD1
O TTL JTAG Test Access Port Test Data Output
I
TTL JTAG Test Access Port Test Logic Reset Input
I
N/A Reserved Inputs for future use. Set HIGH for compatibility reasons.
VDDA
P VDD Analog power supply to PLL.
VSSA
P GND Analog ground to PLL.
VDDD
P VDD Digital power supply.
VSSD
P GND Digital ground.
VDDT
P VDD TTL output power supply.
VSST
VDDP
VDDR
P GND TTL output ground.
PECL Output power supply for PTX.
P VDD PECL Output power supply for RTX.
If use of an output is not necessary, leave the power supply pin open.
N/C
Not connected internally.
G52268-0, Rev 3.3
04/10/01
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Internet: www.vitesse.com
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