VSC7212 Datasheet, PDF (17/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

VIITTEESSSSEE
SEEMMIICCOONNDDUUCCTTOORRCCOORPROPROARTAIOTNION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
LBEN(1:0)
RXP/R
LBTX
PRX+
PRX-
RRX+
RRX-
Figure 11: Parallel Loopback Mode Operation
Clk/Data
Recovery
8
10 8B/10B ⁸ Elastic
Decode ³ Buffer
R(7:0)
IDLE
KCH
ERR
PSDET
RSDET
ªREFCLK
RECEIVER
(dec)
1
0
T(7:0)
8
C/D
0
WSEN
ªREFCLK
11
KCHAR
0
PARLOOP
8
DQ
PTXEN
8B/10B 10
Encode
RTXEN
LBTX
PTX+
PTX-
RTX+
RTX-
TRANSMITTER
Built-In Self Test Operation
Built-In Self Test operation is enabled when the BIST input is HIGH, which causes TMODE(2:0) to be
internally set to 000. Upon entering BIST mode, the transmitter will issue a Word Sync Sequence in order to
recenter the elasticity buffers in the receive channel. Then the transmitter repeatedly sends a simple 256-byte
incrementing data pattern (prior to 8B/10B encoding) followed by three IDLE characters (K28.5). Note that this
incrementing pattern plus three IDLEs will cause both disparities of each data character and the IDLE character
to be transmitted, and contains a sufficient IDLE density for any application requiring IDLE insertion/deletion.
It is up to the user to enable IDLE insertion/deletion if the receiver’s word clock is not frequency locked to the
transmitter’s REFCLK.
The receiver monitors incoming data for this pattern and indicates if any errors are detected. Correct
reception of the pattern is reported on each receiver’s TBERR output, a LOW means the pattern is being
received correctly and a HIGH means that errors are detected. When BIST transitions from LOW to HIGH,
each TBERR output is initialized HIGH. It will be cleared LOW whenever one or more IDLE characters
followed by all 256 data characters are sequentially received without error, and set HIGH whenever a pattern
mis-match or receiver error is encountered. Received data and associated status will be output as in normal
operation. Please note that Serial Loopback mode and receiver output timing mode selection via RMODE(1:0)
operate independently of BIST mode, but BIST mode disables Parallel Loopback mode.
Figure 12: BIST Mode Operation
BIST
Gen ¹
T(7:0)
C/D
WSEN
ªREFCLK
8
0
01
KCHAR
0
BIST
8
DQ
PTXEN
8B/10B 10
Encode
RTXEN
LBTX
LBEN(1:0)
RXP/R
PTX+ PRX+
PTX- PRX-
RTX+ RRX+
RTX- RRX-
TRANSMITTER
Clk/Data
Recovery
PSDET
RSDET
8
10 8B/10B ⁸ Elastic
Decode ³ Buffer
WORDCLK
BIST
Chk
RECEIVER
} ^{From Tx}
Clock Gen
CGERR
1
0
BIST
R(7:0)
IDLE
KCH
ERR
TBERR
G52268-0, Rev 3.3
04/10/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
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