VSC7212 Datasheet, PDF (1/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Features
• ANSI X3T11 Compliant Fibre Channel and IEEE
802.3z Compliant Gigabit Ethernet Transceiver
• Over 2Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• 8B/10B Encoder/Decoder, Optional Encoder/
Decoder Bypass Operation
• “ASIC-Friendly^TM” Timing Options for Transmit-
ter Parallel Input Data
• Elastic Buffer for Chip-to-Chip Cable Deskewing
• Tx/Rx Rate Matching via IDLE Insertion/Deletion
• Compatible with VSC7211, VSC7214 and
VSC7216
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• PECL Rx Signal Detect and Cable Equalization
• Serial Tx-to-Rx and Parallel Rx-to-Tx Internal
Loopback Modes
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 1.0 W
• 100-pin, 14mm TQFP package
General Description
The VSC7212 is an 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high bandwidth
interconnection between busses, backplanes, or other subsystems. A Fibre Channel and Gigabit Ethernet
compliant transceiver provides up to 2.18Gb/s of duplex raw data transfer. The VSC7212 can operate at a
maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at 98MHz).
The VSC7212 contains an 8B/10B encoder, serializer, de-serializer, 8B/10B decoder and elastic buffer which
provide the user with a simple interface for transferring data serially and recovering it on the receive side. The
device can also be configured to operate as a non-encoded 10-bit transceiver with redundant I/O.
VSC7212 Block Diagram
T(7:0)
C/D
WSEN
KCHAR
TRANSMITTER
8
8
DQ
PTXEN
8B/10B 10
Encode
RTXEN
LBTX
PTX+
PTX-
RTX+
RTX-
LBEN(1:0)
RXP/R
PRX+
PRX-
RRX+
RRX-
DUAL
TBC
REFCLKP
REFCLKN
x20/x10
Clock Gen
CAP0 CAP1
Tx Clock
REFCLK
TBERR
REFOUT
TMODE(2:0)
RMODE(1:0)
RECEIVER
Clk/Data
Recovery
PSDET
RSDET
8
10 8B/10B ⁸ Elastic
Decode ³ Buffer
WSI
FLOCK
Channel
Align
RESETN
ENDEC
BIST
TRSTN
TMS
TDI
TCK
JTAG
Boundary
Scan
R(7:0)
IDLE
KCH
ERR
RCLK
RCLKN
WSO
TDO
G52268-0, Rev 3.3
04/10/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
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