VSC7212 Datasheet, PDF (22/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Gigabit Interconnect Chip
Preliminary Data Sheet
VSC7212
Figure 17: Receive Output Timing Waveforms with RMODE = 00 or 01
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
R(7:0), TBERR
KCH, IDLE, ERR
PSDET, RSDET
T_{CQ_max}
T_{CQ_min}
Valid
Valid
T_PER
T_{QC_min}
Valid
Table 12: Receive Output AC Characteristics with RMODE = 00 or 01
Parameters
T_CQ
T_CQ
T_QC
Description
REFCLK Rising Edge to TTL
Output Transition
REFCLK Rising Edge to TTL
Output Transition
TTL Output Transition to
REFCLK Rising Edge
Min
2.58 ns - 0 bc
2.58 ns - 2 bc
T_PER - T_{CQ_max}
Max
5.43 ns - 0 bc
5.43 ns - 2 bc
T_PER - T_{CQ_min}
Units
ns
ns
ns
Conditions
RMODE = 00
bc = Bit Clock
RMODE = 01
bc = Bit Clock
Figure 18: Receive Output Timing Waveforms with RMODE = 10 or 11
RCLK
(DUAL = 0)
RCLK/RCLKN
(DUAL = 1)
R(7:0), TBERR
KCH, IDLE, ERR
PSDET, RSDET
T_{CQ_max}
T_{CQ_min}
Valid
Valid
T_PER
T_{QC_min}
Valid
Table 13: Receive Output AC Characteristics with RMODE = 10 or 11
Parameters
T_CQ
T_QC
DC
Description
RCLK/RCLKN Rising Edge to
TTL Output Transition
TTL Output Transition to RCLK/
RCLKN Rising Edge
RCLK/RCLKN Duty Cycle
Min
-1.25 ns + 4 bc
T_PER -
T_{CQ_max}
50% - 1 ns
Max
1.25 ns + 4 bc
T_PER - T_{CQ_min}
50% + 1 ns
Units
ns
ns
ns
Conditions
RMODE = 10 or 11
bc = Bit Clock
Measured at 1.4 V
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Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01