VSC7212 Datasheet, PDF (13/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
There are four distinct modes of operation defined in Table 6. The first row disables both word alignment
and rate matching. (The fourth and fifth row configurations function identically to the first row.) The second
row configures the VSC7212 to perform rate matching within its receiver without regard to other devices. Word
alignment is disabled and IDLEs will be dropped/duplicated independently of other devices. The third row
configures the part to perform word alignment and rate matching across multiple devices. All receivers will be
aligned per the device driving WSO, and IDLE words will be dropped/duplicated across the aligned channels as
required. The last row configures the part to perform word alignment and disables rate matching. This mode of
operation is appropriate for a frequency-locked application where it desired to align the receive channels
without altering the received data streams.
WSO uses a simple 3-bit serial protocol, synchronous to the Master device’s selected word clock, for
indicating the required synchronization action to other VSC7212s. A steady LOW level indicates no action is
required. ‘101’ indicates that Master device has seen a Word Sync Event. The relative timing relationship
between receiving a Word Sync Event (on all devices together) and seeing ‘101’ on the WSI input in the other
channels allows these channels to word-synchronize with to the Master. ‘110’ indicates that the next IDLE
encountered in the receive data stream should be deleted. ‘111’ indicates that an IDLE should be inserted after
the next IDLE encountered in the receive data stream. Note that the arbitrarily chosen Master device must have
valid input data.
Decoder Bypass Mode
If ENDEC is LOW, the 8B/10B decoder is bypassed and a 10-bit received character, R(9:0), is output from
the receiver. The KCH output becomes R8, and ERR becomes R9. Character alignment is handled differently in
this mode of operation. As mentioned in the “Encoder Bypass Mode” section, the KCHAR input becomes
ENCDET which enables “Comma” detection and re-synchronization when HIGH, and disables re-
synchronization when LOW. Only the ‘0011111xxx’ version of the Comma pattern is recognized when ENDEC
is LOW. The IDLE output becomes COMDET (Comma Detect) which signals detection of the ‘0011111xxx’
Comma pattern in the current 10-bit output character when high. This mode of operation is equivalent to a 10-
bit interface commonly found in serializer/deserializers for the Fibre Channel (e.g., VSC7125) and Gigabit
Ethernet markets (e.g., VSC7135).
The logic used to align multiple devices and perform rate matching is disabled when ENDEC is LOW. In
order for this mode of operation to function without errors, the word clock source as selected by RMODE(1:0)
must be frequency locked to the REFCLK of the remote transmitting device in each channel. This is guaranteed
when RMODE(1:0) = 11. For other choices of RMODE(1:0) the frequency locked condition must be
guaranteed by system design. When DUAL is HIGH and RMODE(1:0) = 10 or 11, the character containing the
‘0011111xxx’ “Comma” pattern is aligned to RCLK/RCLKN so that COMDET will be asserted on the falling
edge of RCLK (rising edge of RCLKN). This is done by adjusting the latency through the elastic buffer, the
recovered clock is never stretched or slivered. When the “Comma” pattern changes the framing boundary, data
characters prior to the assertion of COMDET on the falling edge of RCLK may be corrupted.
G52268-0, Rev 3.3
04/10/01
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