VSC7212 Datasheet, PDF (30/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Gigabit Interconnect Chip
Preliminary Data Sheet
VSC7212
Pin
Name I/O Type
Pin Description
ERRor Detect. When HIGH, an invalid 10-bit character or disparity error
66
ERR
O TTL has been detected and the data on R(7:0) is invalid.
When ENDEC=LOW, this is equivalent to data bit R9.
63
61
RCLK
RCLKN
O
Recovered CLocK Outputs. These outputs are driven from the recovered
TTL clock, at 1/10 or 1/20 the baud rate, as selected by RMODE(1:0) and
DUAL. When unused, RCLK is HIGH and RCLKN is LOW.
36
37
RMODE0
RMODE1
I
Receive Output Data Timing MODE. Determines the timing reference for
TTL R(7:0), IDLE, KCH, ERR, PSDET, RSDET and TBERR, as defined in
Table 5.
Primary Differential Serial RX Inputs. These pins receive the serialized
17
18
PRX+
PRX-
I
PECL
input data when LBEN(1) is LOW and RXP/R is HIGH, otherwise they are
unused. They are internally biased at V_DD/2 through a 3.2KW resistor to the
bias voltage. AC coupling is recommended.
Redundant Differential Serial RX Inputs. These pins receive the serialized
22
23
RRX+
RRX-
I
PECL
input data when LBEN(1) is LOW and RXP/R is LOW, otherwise they are
unused. They are internally biased at V_DD/2 through a 3.2KW resistor to the
bias voltage. AC coupling is recommended.
34
35
LBEN0
LBEN1
I
TTL
Loop Back ENable. These inputs control serial or parallel loopback
configuration as described in Table 8.
RX Input Primary/Redundant serial input select. When LBEN(1) is LOW,
20
RXP/R
I
TTL this input selects PRX+/- as the serial input source when HIGH and RRX+/-
as the serial input source when LOW.
Primary Analog Signal DETect. This output goes HIGH when the
71
PSDET
O
TTL
amplitude on PRX is greater than 200mV and LOW when the input is less
than 100mV. PSDET is not defined when the input is between 100mV and
200mV. Output timing is same as R(7:0).
Redundant Analog Signal DETect. This output goes HIGH when the
69
RSDET
O
TTL
amplitude on RRX is greater than 200mV, LOW when the input is less than
100 mV. RSDET is not defined when the input is between 100mV and
200mV. Output timing is same as R(7:0).
REFCLK Differential Positive and Negative PECL or Single-Ended TTL
Inputs. This rising edge of this clock latches transmit data and control into
30
31
REFCLKP
REFCLKN
I
PECL
the input register. It also provides the reference clock, at 1/10th or 1/20th of
the baud rate to the PLL as selected by DUAL. If TTL, connect to
REFCLKP but leave REFCLKN open. If PECL, connect both REFCLKP
and REFCLKN.
43
REFOUT
O
TTL
REFerence Clock OUTput: This is an output from the clock synthesizer at
the baud rate divided by ten.
13
14
CAP0
CAP1
Loop Filter CAPacitor for Clock Generation PLL. Nominally 0.1 µF,
A Analog amplitude is less than 3V. See the Loop Filter Applications section for more
details.
21
DUAL
I
TTL
DUAL Clock Mode. When LOW, REFCLK and RCLK/RCLKN are 1/10th
the baud rate. When HIGH, they are 1/20th the baud rate.
Page 30
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01