VSC7212 Datasheet, PDF (18/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Gigabit Interconnect Chip
Preliminary Data Sheet
VSC7212
Compatibility with VSC7214 and VSC7211
Care has been taken in the functional definition of the VSC7212 to be sure that it is compatible with the
VSC7211 and VSC7214 at the serial link level, and that the transmitter and receiver low-speed interfaces have
compatible modes of operation. It is strongly recommended that the VSC7212 not be connected in any way
through the WSO and/or WSI pins to a VSC7211 or VSC7214.
Serial Link Compatibility
The VSC7212 uses the same Fibre Channel 8b/10b encoding scheme and the same Word Sync Sequence
used in the VSC7211 and VSC7214. The only difference in serial link operation is that the VSC7211 and
VSC7214 require four consecutive identically-aligned “Comma” patterns to set the character framing boundary,
while the VSC7212 requires a single “Comma.” This means that from the LOSS_OF_SYNC state, the
VSC7212 will make an earlier transition to the RESYNC state (one “Comma” instead of four) as shown in
Figure 9. Once out of the LOSS_OF_SYNC state, there is no difference in receiver behavior in the absence of
data link errors. When transmitting in multiple chip aligned mode from a VSC7212 to a VSC7211 or VSC7214,
use TMODE(2:0)=000 or =1X0 (common transmit interface timing source) to minimize transmitter inter-
channel skew.
Parallel Interface Compatibility
In general the VSC7212 low-speed parallel interfaces can be configured so that there are input and output
signals that are compatible with their VSC7211 and VSC7214 counterparts. On the transmit interface, the
signals T(7:0) and C/D behave identically on the VSC7212 as long as the input timing is referenced to REFCLK
(i.e. TMODE(2:0)=000). On the receive interface, the signals R(7:0), ERR, KCH and IDLE behave identically
on the VSC7212 as long as the output data is centered around REFCLK (RMODE(1:0)=00) or timed to RCLK/
RCLKN (RMODE(1:0)=10). When RMODE(1:0)=10 the VSC7212 RCLK/RCLKN outputs provide four
copies of RCLK/RCLKN, which are equivalent to the VSC7211 and VSC7214 RCLK/RCLKN outputs.
The VSC7212 KCHAR input is no longer a synchronous input timed to REFCLK as on the VSC7211 and
VSC7214. It is a static input used to define the control character encoding mode when C/D=1 as shown in
Table 2.
Operational Mode Compatibility
The VSC7211 and VSC7214 specifications define eight operating modes based on the binary combinations
of the RCLKEN, FLOCK and INDEP inputs. Note that these mode inputs control VSC7211 and VSC7214
receiver operation only, and have no effect on transmitter operation. For each of these modes, the equivalent
VSC7212 receiver configuration is presented. There is no INDEP input in the VSC7212.
VSC7214 MODE 0: RCLKEN=LOW, FLOCK=LOW, INDEP=LOW
Receiver R(7:0), ERR, KCH and IDLE outputs are synchronous to REFCLK, IDLE insertion/deletion is
enabled, and multiple receivers are word aligned. The VSC7212 should be configured with RMODE(1:0)=00,
FLOCK=0, and WSI connected to its own WSO or to the WSO of another VSC7212 if multiple devices are to
be used in parallel. The WSI connection allows IDLE insertion/deletion to occur in parallel across all word-
aligned devices.
Page 18
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
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Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01