VSC7212 Datasheet, PDF (3/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Transmitter Functional Description
Transmitter Data Bus
The VSC7212 transmitter has an 8-bit input transmit data character, T(7:0), and two control inputs, C/D and
WSEN. The C/D input determines whether a normal data character or a special “K-character” is transmitted,
and the WSEN input initiates transmission of a 16-character “Word Sync Sequence” used to align the receiver.
These data and control inputs are clocked either on the rising edge of REFCLK, on the rising edge of TBC, or
within the data eye formed by TBC (“ASIC-Friendly” timing). The transmit interface mode is controlled by
TMODE(2:0) as shown in Table 1.
When used, TBC must be frequency locked to REFCLK. No phase relationship is assumed. A small skew
buffer is provided to tolerate phase drift between TBC and REFCLK. This buffer is recentered by the RESETN
input, and the total phase drift after recentering must be limited to +/- 180× (where 360× is one character time).
The VSC7212 has an error output, TBERR, that is asserted HIGH to indicate that the phase drift between TBC
and REFCLK has accumulated to the point that the elastic limit of the skew buffer has been exceeded and a
transmit data character has been either dropped or duplicated. This error can not occur when input timing is
referenced to REFCLK. The TBERR output timing is identical to the low-speed receiver outputs, as selected by
RMODE(1:0) in Table 5.
Table 1: Transmit Interface Input Timing Mode
TMODE(2:0)
000
001
01X
10X
11X
Input Timing Reference
REFCLK Rising Edge
Reserved
TBC Rising Edge
TBC Data Eye
The following figures show the possible relationships between data and control inputs and the selected
input timing source. Figure 2 shows how REFCLK is used as an input timing reference. This mode of operation
is also used in the VSC7211 and VSC7214. Figure 3 and Figure 4 show how TBC is used as an input timing
reference. When TBC is used to define a data eye as shown in Figure 4, it functions as an additional data input
that simply toggles every cycle.
Note that the REFCLK and TBC inputs are not used directly to clock the input data. Instead, an internal
PLL generates edges aligned with the appropriate clock. The arrows on the rising edges of these signals define
the reference edge for the internal phase detection logic. An internal clock is generated at 1/10 the serial
transmit data rate that is locked to the selected input timing source. This is an especially important issue when
DUAL is HIGH and input timing is referenced to REFCLK, since the falling edge is NOT used. The internal
clock active edges are placed coincident with the REFCLK rising edges and halfway between the REFCLK
rising edges in this mode.
G52268-0, Rev 3.3
04/10/01
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