VSC7212 Datasheet, PDF (24/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

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Gigabit Interconnect Chip
Preliminary Data Sheet
VSC7212
Figure 20: REFCLK Timing Waveforms
REFCLK
T_H
T_L
V_IH(MIN)
V_IL(MAX)
Table 15: Reference Clock Requirements
Parameters
Description
FR
Frequency range
FO
Frequency offset
DC
T_H,T_L
T_RCR,T_RCF
REFCLK
Jitter
REFCLK duty cycle
REFLCK and TBC pulse width
REFCLK rise and fall time
REFCLK Jitter Power
3MHz
∫ ^PhaseNoise
100 H z
Min Max
98 136
49
68
-200 200
35
65
3
—
—
1.5
— 100
Units
MHz
MHz
ppm
%
ns
ns
ps
Conditions
DUAL = 0
DUAL = 1
| REFCLK (Tx) - REFCLK (Rx) | =
max offset between Tx and Rx device
REFCLKs on one serial link
Measured at 1.4V
Between V_IL(MAX) and V_IH(MIN)
RMS for 10^-12 Bit Error Ratio with zero
length external path, tested on a sample
basis
Page 24
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800)-VITESSE • FAX: [phone] • Email: [e-mail]
Internet: www.vitesse.com
G52268-0, Rev 3.3
04/10/01