VSC7212 Datasheet, PDF (21/34 Pages) Vitesse Semiconductor Corporation – Gigabit Interconnect Chip

VIITTEESSSSEE
SEEMMIICCOONNDDUUCCTTOORRCCOORPROPROARTAIOTNION
Preliminary Data Sheet
VSC7212
Gigabit Interconnect Chip
Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing)
TBC
Internal Clock
(from PLL)
T(7:0)
C/D
Valid
WSEN
T_S
Valid
T_S
Valid
Table 10: Transmit Input AC Characteristics with TMODE = 11X
Parameters
Description
Min
Max Units
Conditions
T_S
Input Skew relative to the rising
edge of TBC
—
Measured between the valid data
2.0
bc level of the input and the 1.4V point
of TBC
Figure 16: Transmit Serial Timing Waveforms
TX+, TX-
Internal Clock
(from PLL)
T_SDR, T_SDF
T_LAT
TX0
Table 11: Transmit Serial AC Characteristics
Parameters
Description
T_SDR, T_SDF
T_LAT
T_J
T_DJ
TX+/- rise and fall time
Latency, REFCLK to TX0
Latency, TBC to TX0
Serial data output
Total Jitter (p-p)
Serial data output
Deterministic Jitter (p-p)
Min
—
22bc+0.2ns
36bc+0.0ns
—
—
Max
330
22bc+0.8ns
38bc+0.3ns
192
80
Units
ps
bc + ns
ps
ps
Conditions
Between V_OL(MAX) and
V_OH(MIN)
ENDEC=1 TMODE=000
ENDEC=1 TMODE=10X
IEEE 802.3z Clause 38.69,
Tested on a sample basis
IEEE 802.3z Clause 38.69,
Tested on a sample basis
G52268-0, Rev 3.3
04/10/01
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